– vi –
LIST OF FIGURES (1/4)
Figure No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Selecting MBE = 0 Mode and MBE = 1 Mode.......................................................................
Configuration of Data Memory and Addressing Ranges of Respective Addressing Modes .
Updating Address of Static RAM...........................................................................................
Example of Using Register Banks.........................................................................................
Configuration of General-Purpose Registers (in 4-bit processing)........................................
Configuration of General-Purpose Registers (in 8-bit processing)........................................
m
PD753017 I/O Map .............................................................................................................
26
28
32
39
41
42
45
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
Format of Stack Bank Select Register ..................................................................................
Configuration of Program Counter ........................................................................................
Program Memory Map...........................................................................................................
Data Memory Map.................................................................................................................
Configuration of Display Data Memory..................................................................................
Configuration of General-Purpose Register ..........................................................................
Configuration of Register Pair ...............................................................................................
Accumulator ..........................................................................................................................
Configuration of Stack Pointer and Stack Bank Select Register...........................................
Data Saved to Stack Memory (MkI Mode) ............................................................................
Data Restored from Stack Memory (MkI Mode)....................................................................
Data Saved to Stack Memory (MkII Mode) ...........................................................................
Data Restored from Stack Memory (MkII Mode)...................................................................
Configuration of Program Status Word .................................................................................
Configuration of Bank Select Register ..................................................................................
52
53
55
61
63
64
64
65
66
67
67
68
68
69
73
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
Data Memory Address of Digital Port ....................................................................................
Configuration of Ports 0 and 1 ..............................................................................................
Configuration of Ports 3 and 6 ..............................................................................................
Configuration of Ports 2 and 7 ..............................................................................................
Configuration of Ports 4 and 5 ..............................................................................................
Format of Each Port Mode Register......................................................................................
Format of Pull-up Resistor Register ......................................................................................
I/O Timing of Digital I/O Port .................................................................................................
ON Timing of Internal Pull-up Resistor Connected via Software ..........................................
Block Diagram of Clock Generation Circuit ...........................................................................
Format of Processor Clock Control Register.........................................................................
Format of System Clock Control Register .............................................................................
External Circuit of Main System Clock Oscillation Circuit .....................................................
External Circuit of Subsystem Clock Oscillation Circuit ........................................................
Incorrect Example of Connecting Resonator ........................................................................
Subsystem Clock Oscillation Circuit......................................................................................
Format of Suboscillation Circuit Control Register (SOS).......................................................
Selecting System Clock and CPU Clock ...............................................................................
75
77
78
78
79
81
87
88
89
90
93
94
95
95
96
99
101
103