![](http://datasheet.mmic.net.cn/380000/-PD703100_datasheet_16744885/-PD703100_2.png)
P art Number
μPD70F3102
μPD703101
μPD703100
Internal R O M
Flash Memory
Mask ROM
ROMless
P ac k age
144-pin plastic QFP (fine pitch) (20 x 20 mm)
144-pin plastic QFP (fine pitch) (20 x 20 mm)
144-pin plastic QFP (fine pitch) (20 x 20 mm)
F E A T U R E D E S C R I P T I O N
C P U
—
Highly integrated microcontroller
–
32-bit arithmetic logic unit (ALU)
–
Thirty-two general-purpose 32-bit registers
–
Five-stage pipeline
—
Single-cycle 16 x 16 — 32-bit and
32 x 32 — 64-bit signed/unsigned
multiply instruction
—
Five divide instructions
—
Three single-cycle byte swap instructions
—
Powerful RISC instruction set
–
81 RISC instructions: 16- and 32-bit
–
Two-cycle MAC function for DSP applications
–
Saturated arithmetic instructions (over/
underflow detection function)
–
Single-cycle, 32-bit shift instructions
–
Bit manipulation instructions
–
Load and store instructions with
8-/16-/32-bit signed/unsigned data
MEMO R Y
—
Single-cycle internal 128KB flash memory
or 96KB mask ROM
—
Single-cycle internal 4KB RAM
—
32MB external memory space
—
Idle state insertion for slow memory
EX T ER NA L B US INT ER FA C E
—
24-bit address; 16-bit data bus with two cycles
—
Programmable and external wait functions
—
Idle state insertion for slow memory
INT ER R UP T S
—
47 maskable interrupts plus NMI
—
Eight programmable priority levels on all
interrupts
—
Specifiable rising and/or falling edge detection
—
32 software traps
D MA C O NT R O L L ER
—
Four channels with 8-/16-bit transfer width
—
Single/single-step/block transfer mode
—
Memory to memory and memory to I/O
MEMO R Y C O NT R O L L ER
—
DRAM controller
–
EDO/fast-page mode
–
DRAM direct interface (RAS 4x, LCAS, UCAS)
–
Refresh controller
—
ROM controller
–
Page mode
P ER IP HER A L S
—
114 I/Os plus nine input-only reassignable pins
—
Real-time pulse unit
–
Six-channel 16-bit timer/event counter with
24 capture/compare registers
–
Two-channel 16-bit interval timer with two
compare registers
–
One-channel watch counter
–
One-channel watchdog timer
—
Serial interface
–
Two-channel UART/clocked serial interface
–
Two-channel clocked serial interface
–
Three dedicated baud rate generators
—
Clock generator
–
Internal PLL (5x, 1x, 1/2x)
–
Direct clock input
—
Analog interface
–
Eight-channel A/D converter with 10-bit
resolution
O T HER
—
Power saving features
–
Halt/idle/stop modes
–
Clock output inhibit mode
—
Fully static operation
—
Dual power supply
–
5V for external pins
–
3.3V for internal pins
–
5V for A/D converter
O R D E R I N G
I N F O R M A T I O N
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or visit our Web site at
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Document # U12481EU2V0PB00