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參數(shù)資料
| 型號(hào)： | XSC7400RX400PE |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 70K |
| 代理商： | XSC7400RX400PE |
MPC7400 Part Number Specifications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1.4.2.3 L2 Clock AC Specifications
Table 10 provides the L2CLK Output AC Timing SpeciTcations for the MPC7400 part described in this Part Number SpeciTcation
.
1.4.2.4 L2 Bus AC Specifications
Table 11 provides the L2 Bus Interface AC Timing SpeciTcations for the frequencies described in this Part Number SpeciTcation.
Table 10. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3)
Parameter
Symbol
400 MHz
450 MHz
Unit
Notes
Min
Max
Min
Max
L2CLK frequency
f
L2CLK
150
400
150
450
MHz
1
L2CLK cycle time
t
L2CLK
2.5
6.67
2.22
6.67
ns
L2CLK duty cycle
t
CHCL
/t
L2CLK
50
50
%
2
Internal DLL-relock time
640
—
640
—
L2CLK
4
DLL capture window
±200
±200
ns
5
Notes
See General hardware specification.
:
Table 11. L2 Bus Interface AC Timing Specifications
At Vdd=AVdd=L2AVdd= 2.15V±50mV; 0
TBD
￡
Tj
￡
65°C, L2OVdd = 3.3V±165mV and L2OVdd = 2.5V±100mV, Times for L2OVdd=1.8V±100mV are
Parameter
Symbol
400, 450
MHz
Unit
Notes
Min
Max
L2SYNC_IN rise and fall time
t
L2CR
& t
L2CF
—
1.0
ns
1
Setup Times:
Data and parity
t
DVL2CH
1.5
—
ns
2
Input Hold Times:
Data and parity
t
DXL2CH
—
0.0
ns
2
Valid Times:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
t
L2CHOV
-
-
-
-
2.5
3.0
3.5
4.0
ns
3,4
Output Hold Times
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
t
L2CHOX
0.6
1.0
1.4
1.8
-
-
-
-
ns
3
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