參數(shù)資料
型號: XRT86VL34IB
廠商: Exar Corporation
文件頁數(shù): 67/155頁
文件大小: 0K
描述: IC LIU/FRAMER T1/E1/J1 4CH 225BG
標準包裝: 84
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT86VL34
14
REV. V1.2.1
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
FASTSYNC
R/W
0
Faster Sync Algorithm
This bit is used to specify one of the synchronization criteria that the
Receive T1 Framer block employs. If this “Faster Sync Algorithm” is
enabled, the Receive T1 Framer Block will declare synchronization
earlier. The table below specifies the number of consecutive frames
with correct F-bits that the T1 Receive framer must receive in order
to declare “SYNC” when FASTSYNC is enabled or disabled.
0 - Disables FASTSYNC feature.
1 - Enables FASTSYNC feature.
2-0
FSl[2:0]
R/W
000
T1 Framing Mode Select [2:0]
These three bits permit the user to select the exact T1 framing format
that the channel is to operate in.
Bit 2 is MSB and Bit 0 is LSB. The following table shows the five dif-
ferent framing formats that can be selected by configuring these
three bits accordingly.
NOTE: Changing Framing formats 'on the fly' will cause the Receive
T1 Framer block to undergo a “Reframe” event.
TABLE 4: FRAMING SELECT REGISTER (FSR)
HEX ADDRESS: 0Xn107
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
Framing
FastSync
= 0
FastSync
= 1
ESF
96
48
SF
48
24
N
48
24
SLC
96
48
24
Framing
FS[2]
FS[1]
FS[0]
ESF
0
X
SF
1
0
1
N
1
0
T1DM
1
SLC
96
1
0
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