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參數(shù)資料
| 型號： | XRT83L38IB-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 68/87頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 225BGA |
| 標準包裝： | 84 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA |
| 供應商設備封裝： | 225-BGA（19x19） |
| 包裝： | 托盤 |
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XRT83L38
67
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x81h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly.
During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, register 0x81h can be broken down into two sub-registers with the MSB being bits
D[7:3] and the LSB being bits D[2:0] as shown in Figure 25. Note: Bit D[7] is a reserved bit.
FIGURE 25. REGISTER 0X81H SUB REGISTERS
Programming Examples:
Example 1: Changing bits D[7:3]
If bits D[7:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[2:0]
If bits D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (MSB) and then change bits D[2:0] (LSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION
REGISTER ADDRESS
10000001
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D7
Reserved
R/W
0
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Clock Selection Bits
ExLOS, ICT
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相關代理商/技術參數(shù) |
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|---|---|
| XRT83L38IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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| XRT83SH314_0610 | 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314ES | 功能描述:外圍驅(qū)動器與原件 - PCI 14 CHT1/E1LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83SH314IB | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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