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XRT79L71
PRELIMINARY
23
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
1.4.15
The Receive FEAC Controller Block (DS3, C-bit Parity Applications Only)
The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &
Control) Messages from the remote terminal equipment.
NOTE: The Receive FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity
Framing format.
1.4.16
The Receive PPP Packet Processor Block
The purpose of the Receive PPP Packet Processor block is to extract out the payload data (being carried by
the incoming DS3/E3 data-stream) and to perform the following operations on it.
Identification/Location of boundaries of incoming PPP packets
Computation and Verification of either the CRC-16 or CRC-32 values within the incoming PPP Packets
To Parse through the contents of each inbound packet for any occurrences of the values 0x7D5E and
0x7D5D and to character de-stuff (or replace) these values with strings of 0x7E and 0x7D, respectively
To terminate any incoming Flag Sequence octets
To flag the occurrence of any incoming RUNT packets
To flag the occurrence of any incoming Aborted Packets
1.4.17
The Receive Overhead Data Output Interface Block
The purpose of the Receive Overhead Data Output Interface block is to permit the user to extract out the
overhead bits (within the incoming DS3/E3 data-stream) and to route this data to some off-chip System-Side
Terminal Equipment circuitry.
1.4.18
The Receive POS-PHY Interface Block
The purpose of the Receive POS-PHY Interface block is to provide a standard Saturn POS-PHY Level 2 or 3
compliant interface to the Link Layer Processor, for reading in the contents of all inbound PPP Packets, from
the Receive FIFO (RxFIFO).
The Receive POS-PHY Interface block can be configured to operate with either an 8 or 16-bit wide Receive
POS-PHY Data Bus.
NOTES:
1.
The Receive POS-PHY Interface Block supports POS-PHY Level 3 from a signaling stand-point. The Receive
POS-PHY Interface block (within the XRT79L71) still only supports a 16-bit wide (not 32-bit wide) POS-PHY Data
Bus and only operates up to 50MHz (not 104MHz).
2.
The Receive POS-PHY Interface Block can be configured to support either Out-of-Band Addressing or In-Band
Addressing for Device Selection to READ. However, since the XRT79L71 is a single-channel device, we strongly
recommend that the user only use Out-of-Band Addressing for Device Selection whenever it is designed into a
Multi-PHY systemin which multiple PHY Layer devices are sharing the same POS-PHY Bus.
1.4.19
A more detailed Functional/Architectural Description of the XRT79L71, when configured to
operate in the PPP Mode can be found in the document (79L71_Arch_Descr_PPP.pdf)
(Architectural/Functional Description of the XRT79L71 1-Channel DS3/E3 ATM UNI/PPP/Clear-Channel
Framer with LIU IC - PPP Mode Applications).
2.0
MICROPROCESSOR INTERFACE
The Microprocessor Interface of the XRT79L71 can be configured to support a wide variety of modes. These
modes are listed below.
Intel-Asynchronous Mode
Motorola-Asynchronous Mode
Intel X86 Mode