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XRT75VL00D
41
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
0x07
R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
ator as shown in the table below.
0
D1
JATx/Rx
Writing a “1” to this bit selects the Jitter Attenuator in
the Transmit Path. A “0” selects in the Receive Path.
0
D2
JA1
This bit along with the JA0 configures the Jitter Atten-
uator as shown in the table.
0
D3
PNTRST
Setting this bit to “1” resets the Read and Write point-
ers of the jitter attenuator FIFO.
0
D4
DFLCK
Set this bit to "1" to disable the SONET APS Recov-
ery Time of the PLL. When this bit is "0", the APS
Recovery Time is enabled. This helps to reduce the
time for the PLL to lock to the incoming frequency
when the Jitter Attenuator switches to narrow band.
This is required for SONET to DS-3 Mapping/Demap-
ping De-Synchronization applications.
0
0x08
Reserved
ADDRESS
(HEX)
TYPE
BIT
LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
0x20
R/W
D0
INTEN
Bit 0 = INTEN Writing a “1” to this bit enables the
interrupts.
0
0x21
Read
Only
D0
INTST
Bit 0 = INTST bit is set to “1” if an interrupt service is
required. The source level interrupt status register is
read to determine the cause of interrupt.
0
0x22 -
0x2F
Reserved
0x30
Reset
Upon
Read
D[7:0]
PRBSmsb
PRBS error counter MSB [15:8]
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
DEFAULT
VALUE(BIN)
JA0
0
Mode
16 bit FIFO
32 bit FIFO
JA1
0
1
128 bit FIFO
0
1
Disable Jitter
Attenuator