-INTA 8085 CPU -<" />
參數(shù)資料
型號: XR88C681CJTR-F
廠商: Exar Corporation
文件頁數(shù): 28/101頁
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 44PLCC
標準包裝: 500
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
其它名稱: XR88C681CJTR-F-ND
XR88C681
32
Rev. 2.11
X1
X2
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
-INTA
8085 CPU
-IO/M
-RD
-WR
-MEMR
ALE
C
AD0 - AD7
A8 - A15
Address
Decoder
A0 - A3
A4 - A7
A8 - A15
D0 - D7
A0 - A3
-CS
74LS373
1D - 8D
1Q - 8Q
-RD
-WR
XR88C681
-MEMW
-CS_DUART
-CS_OTHER_IC
Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped).
The DUART’s -INTR pin was deliberately omitted from
Figure 9, because its use will be addressed in Figure 10
and
Figure 11.
8085 CPU Module Interrupt Structure
The 8085 CPU supports both Direct and “External”
Vectored Interrupt processing. The 8085 has 4 maskable
interrupt request inputs (RST 5.5, RST 6.5, RTS 7.5, and
INTR), and 1 non-maskable interrupt request input
(TRAP). When discussing interfacing for the interrupt
servicing of peripheral devices such as the DUART, we
are only concerned with the maskable interrupt request
inputs. Of the four maskable interrupt request inputs;
three of these inputs support “Direct Interrupt”
processing.
The remaining one interrupt request
supports “External Vectored Interrupt” processing.
Table 11 lists these Interrupt Request inputs and their
characteristics/features.
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