- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375052 > XQ4085XL-1HQ432M (Xilinx, Inc.) QML High-Reliability FPGAs PDF資料下載
參數(shù)資料
| 型號： | XQ4085XL-1HQ432M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QML High-Reliability FPGAs |
| 中文描述： | QML第高可靠性的FPGA |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | XQ4085XL-1HQ432M |
QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
11
R
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out
(1,2,3)
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
ICKOF
Global low skew clock to output using OFF
(4)
XQ4013XL
1.5
8.6
-
ns
XQ4036XL
2.0
9.8
-
ns
XQ4062XL
2.3
11.3
-
ns
XQ4085XL
2.5
-
9.5
ns
T
SLOW
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
3.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load.
4.
OFF = Output Flip-Flop
For output SLOW option add
All Devices
3.0
3.0
3.0
ns
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
ICKEOF
Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6.
XQ4013XL
1.3
7.4
-
ns
XQ4036XL
1.2
8.1
-
ns
XQ4062XL
1.2
9.9
-
ns
XQ4085XL
1.3
-
8.5
ns
Notes:
1.
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load.
2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ4085XL-1HQ432N | QML High-Reliability FPGAs |
| XQ4013XL-1HQ432N | QML High-Reliability FPGAs |
| XQ4013XL-1HQ475M | QML High-Reliability FPGAs |
| XQ4013XL-1HQ475N | QML High-Reliability FPGAs |
| XQ4013XL-1PG228M | QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4085XL-1HQ432N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4085XL-1HQ475M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4085XL-1HQ475N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4085XL-1PG228M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4085XL-1PG228N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。