參數(shù)資料
型號(hào)： XQ4062XL-3PQ228N
廠商： Xilinx, Inc.
英文描述： QML High-Reliability FPGAs
中文描述： QML第高可靠性的FPGA
文件頁(yè)數(shù)： 6/22頁(yè)
文件大小： 162K
代理商： XQ4062XL-3PQ228N
QPRO XQ4000XL Series QML High-Reliability FPGAs
6
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and expressed in nanosec-
onds unless otherwise noted.
CLB Switching Characteristics
Symbol
Combinatorial Delays
T
ILO
T
IHO
T
ITO
T
HH0O
T
HH1O
T
HH2O
T
CBYP
CLB Fast Carry Logic
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
NET
Sequential Delays
T
CKO
T
CKLO
Setup Time Before Clock K
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
Description
-3
-1
Units
Min
Max
Min
Max
F/G inputs to X/Y outputs
F/G inputs via H
’
to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via D
IN
/H2 via H to X/Y outputs
C inputs via EC, D
IN
/H2 to YQ, XQ output (bypass)
-
-
-
-
-
-
-
1.6
2.7
2.9
2.5
2.4
2.5
1.5
-
-
-
-
-
-
-
1.3
2.2
2.2
2.0
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
Carry net delay, C
OUT
to C
IN
-
-
-
-
-
-
2.7
3.3
2.0
2.8
0.26
0.32
-
-
-
-
-
-
2.0
2.5
1.5
2.4
0.20
0.25
ns
ns
ns
ns
ns
ns
Clock K to flip-flop outputs Q
Clock K to latch outputs Q
-
-
2.1
2.1
-
-
1.6
1.6
ns
ns
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via D
IN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F/G
C
IN
input via F/G and H
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
-
-
-
-
-
-
-
-
-
-
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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