- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375052 > XQ4062XL-3CB228N (Xilinx, Inc.) QML High-Reliability FPGAs PDF資料下載
參數(shù)資料
| 型號： | XQ4062XL-3CB228N |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QML High-Reliability FPGAs |
| 中文描述： | QML第高可靠性的FPGA |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | XQ4062XL-3CB228N |
QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
17
R
XQ4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). For Propagation
Delays, slew-rate = fast unless otherwise noted. Values are
expressed in nanoseconds unless otherwise noted.
Symbol
Description
-3
-1
Units
Min
Max
Min
Max
Clocks
T
CH
T
CL
Clock High
3.0
-
2.5
-
ns
Clock Low
3.0
-
2.5
-
ns
Propagation Delays
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OFPF
T
OKFPF
Setup and Hold Times
Clock (OK) to pad
-
5.0
-
3.8
ns
Output (O) to pad
-
4.1
-
3.1
ns
High-Z to pad High-Z (slew-rate independent)
-
4.4
-
3.0
ns
High-Z to pad active and valid
-
4.1
-
3.3
ns
Output (O) to pad via fast output MUX
-
5.5
-
4.2
ns
Select (OK) to pad via fast MUX
-
5.1
-
3.9
ns
T
OOK
T
OKO
T
ECOK
T
OKEC
Global Set/Reset
Output (O) to clock (OK) setup time
0.5
-
0.3
-
ns
Output (O) to clock (OK) hold time
0
-
0
-
ns
Clock Enable (EC) to clock (OK) setup time
0
-
0
-
ns
Clock Enable (EC) to clock (OK) hold time
0.3
-
0.1
-
ns
T
MRW
T
RPO
Minimum GSR pulse width
Delay from GSR input to any pad
(2)
19.8
-
15.0
-
ns
XQ4013XL
-
20.5
-
-
ns
XQ4036XL
-
27.1
-
-
ns
XQ4062XL
-
33.7
-
-
ns
XQ4085XL
-
-
29.5
ns
Slew Rate Adjustment
T
SLOW
Notes:
1.
Output timing is measured at ~50% V
CC
threshold, with 50 pF external capacitive loads.
2.
Indicates Minimum Amount of Time to Assure Valid Data.
For output SLOW option add
-
3.0
-
2.0
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ4062XL-3CB240M | QML High-Reliability FPGAs |
| XQ4062XL-3CB240N | QML High-Reliability FPGAs |
| XQ4062XL-3CB432M | QML High-Reliability FPGAs |
| XQ4062XL-3CB432N | QML High-Reliability FPGAs |
| XQ4062XL-3CB475M | QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4062XL-3CB240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4062XL-3CB240N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4062XL-3CB432M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4062XL-3CB432N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4062XL-3CB475M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。