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參數(shù)資料
| 型號(hào)： | XQ4036XL-1HQ475M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QML High-Reliability FPGAs |
| 中文描述： | QML第高可靠性的FPGA |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | XQ4036XL-1HQ475M |
QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5
R
XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Global Buffer Switching Characteristics
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GLS
Delay from pad through Global Low Skew buffer, to any
clock K
XQ4013XL
0.6
3.6
-
ns
XQ4036XL
1.1
4.8
-
ns
XQ4062XL
1.4
6.3
-
ns
XQ4085XL
1.6
-
5.7
ns
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
XQ4013XL
0.4
2.4
-
ns
XQ4036XL
0.3
3.1
-
ns
XQ4062XL
0.3
4.9
-
ns
XQ4085XL
0.4
-
4.7
ns
Symbol
Description
Device
All
Min
-3
-1
Units
Max
Max
T
GE
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
XQ4013XL
0.7
2.4
-
ns
XQ4036XL
0.9
4.7
-
ns
XQ4062XL
1.2
5.9
-
ns
XQ4085XL
1.3
-
5.5
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ4036XL-1HQ475N | QML High-Reliability FPGAs |
| XQ4036XL-1PG228M | QML High-Reliability FPGAs |
| XQ4036XL-1PG228N | QML High-Reliability FPGAs |
| XQ4036XL-1PG240M | QML High-Reliability FPGAs |
| XQ4036XL-1PG240N | QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4036XL-1HQ475N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4036XL-1PG228M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4036XL-1PG228N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4036XL-1PG240M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4036XL-1PG240N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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