參數(shù)資料
型號： XQ4025E-3PG196N
廠商： Xilinx, Inc.
英文描述： QML High-Reliability FPGAs
中文描述： QML第高可靠性的FPGA
文件頁數(shù)： 14/36頁
文件大?。?/td> 285K
代理商： XQ4025E-3PG196N
QPRO XQ4000E/EX QML High-Reliability FPGAs
14
www.xilinx.com
1-800-255-7778
DS021 (v2.2) June 25, 2000
Product Specification
R
XQ4000E IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
Propagation Delays (TTL Inputs)
(1)
Description
Device
-3
-4
Units
Min
Max
Min
Max
T
PID
T
PLI
T
PDLI
Pad to I1, I2
All devices
-
2.5
-
3.0
ns
Pad to I1, I2 via transparent input latch, no delay
All devices
-
3.6
-
4.8
ns
Pad to I1, I2 via transparent FCL and input latch,
with delay
XQ4005E
-
-
-
10.8
ns
XQ4010E
-
10.8
-
11.0
ns
XQ4013E
-
11.2
-
11.4
ns
XQ4025E
-
-
-
13.8
ns
Propagation Delays (CMOS Inputs)
(1)
T
PIDC
T
PLIC
T
PDLIC
Pad to I1, I2
All devices
-
4.1
-
5.5
ns
Pad to I1, I2 via transparent input latch, no delay
All devices
-
8.8
-
6.8
ns
Pad to I1, I2 via transparent FCL and input latch,
with delay
XQ4005E
-
-
-
16.5
ns
XQ4010E
-
14.0
-
17.5
ns
XQ4013E
-
14.4
-
18.0
ns
XQ4025E
-
-
-
20.8
ns
Propagation Delays (TTL Inputs)
T
IKRI
T
IKLI
Hold Times
(2)
Clock (IK) to I1, I2 (flip-flop)
All devices
-
2.8
-
5.6
ns
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
4.0
-
6.2
ns
T
IKPI
T
IKPID
T
IKEC
T
IKECD
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Pad to clock (IK), no delay
All devices
0
-
0
-
ns
Pad to clock (IK), with delay
All devices
0
-
0
-
ns
Clock enable (EC) to clock (K), no delay
All devices
1.5
-
1.5
-
ns
Clock enable (EC) to clock (K), with delay
All devices
0
-
0
-
ns
相關(guān)PDF資料
PDF描述
XQ4025E-4BG196M QML High-Reliability FPGAs
XQ4025E-4BG196N QML High-Reliability FPGAs
XQ4025E-4HQ196M QML High-Reliability FPGAs
XQ4025E-4HQ196N QML High-Reliability FPGAs
XQ4025E-4PG196M QML High-Reliability FPGAs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XQ4025E-4BG191M 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4025E-4BG191N 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4025E-4BG196M 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs
XQ4025E-4BG196N 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs
XQ4025E-4CB191M 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*