參數(shù)資料
型號(hào)： XQ4025E-3BG196N
廠商： Xilinx, Inc.
英文描述： QML High-Reliability FPGAs
中文描述： QML第高可靠性的FPGA
文件頁(yè)數(shù)： 3/36頁(yè)
文件大小： 285K
代理商： XQ4025E-3BG196N
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
3
R
XQ4000E Recommended Operating Conditions
(1,2)
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Max
Units
V
CC
Supply voltage relative to GND, T
J
=
–
55
°
C to +125
°
C
Supply voltage relative to GND, T
C
=
–
55
°
C to +125
°
C
High-Level Input Voltage
Plastic
4.5
5.5
V
Ceramic
4.5
5.5
V
V
IH
TTL inputs
2.0
V
CC
100%
V
CMOS inputs
70%
V
CC
V
V
IL
Low-Level Input Voltage
TTL inputs
0
0.8
CMOS inputs
0
20%
V
CC
ns
T
IN
Input signal transition time
-
250
Notes:
1.
2.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°
C.
Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
Symbol
Description
Min
Max
Units
V
OH
High-level output voltage @ I
OH
=
–
4.0 mA, V
CC
min
High-level output voltage @ I
OH
=
–
1.0 mA, V
CC
min
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min
(1)
TTL outputs
2.4
-
V
CMOS outputs
V
CC
–
0.5
-
-
V
V
OL
TTL outputs
0.4
V
CMOS outputs
-
0.4
V
I
CCO
I
L
C
IN
I
RIN
I
RLL
Quiescent FPGA supply current
(2)
-
50
mA
Input or output leakage current
–
10
+10
μ
A
pF
Input capacitance (sample tested)
Pad pull-up (when selected) at V
IN
= 0V (sample tested)
(3)
Horizontal longline pull-up (when selected) at logic Low
(3)
-
16
–
0.02
–
0.25
mA
0.2
2.5
mA
Notes:
1.
2.
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at V
CC
or GND, and the FPGA configured
with the development system Tie option.
Characterized Only.
3.
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