- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375044 > XQ2V1000-4BG575M (Xilinx, Inc.) QPro Virtex-II 1.5V Military QML Platform FPGAs PDF資料下載
參數(shù)資料
| 型號(hào)： | XQ2V1000-4BG575M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA |
| 文件頁(yè)數(shù)： | 12/128頁(yè) |
| 文件大?。?/td> | 2738K |
| 代理商： | XQ2V1000-4BG575M |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
QPro Virtex-II 1.5V Military QML Platform FPGAs
12
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in
Figure 8
and
Figure 9
. Each
bank has multiple V
CCO
pins, all of which must be con-
nected to the same voltage. This voltage is determined by
the output standards in use.
Some input standards require a user-supplied threshold
voltage (V
REF
), and certain user-I/O pins are automatically
configured as V
REF
inputs. Approximately one in six of the
I/O pins in the bank assume this role.
V
REF
pins within a bank are interconnected internally, and
consequently only one V
REF
voltage can be used within
each bank. However, for correct operation, all V
REF
pins in
the bank must be connected to the external reference volt-
age source.
The V
CCO
and the V
REF
pins for each bank appear in the
device pinout tables. Within a given package, the number of
V
REF
and V
CCO
pins can vary depending on the size of
device. In larger devices, more I/O pins convert to V
REF
pins. Since these are always a superset of the V
REF
pins
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
REF
pins for the largest device anticipated must be con-
nected to the V
REF
voltage and are not used for I/O. In
smaller devices, some V
CCO
pins used in larger devices do
not connect within the package. These unconnected pins
can be left unconnected externally, or, if necessary, they can
be connected to V
CCO
to permit migration to a larger device.
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bidirectional standards in the same bank:
1.
Combining output standards only.
Output standards
with the same output V
CCO
requirement can be
combined in the same bank.
Compatible example:
SSTL2_I and LVDS_25_DCI outputs
Incompatible example:
SSTL2_I (output V
= 2.5V) and
LVCMOS33 (output V
CCO
= 3.3V) outputs
2.
Combining input standards only.
Input standards
with the same input V
CCO
and input V
REF
requirements
can be combined in the same bank.
Compatible example:
LVCMOS15 and HSTL_IV inputs
Incompatible example:
LVCMOS15 (input V
CCO
= 1.5V) and
LVCMOS18 (input V
CCO
= 1.8V) inputs
Incompatible example:
HSTL_I_DCI_18 (V
REF
= 0.9V) and
HSTL_IV_DCI_18 (V
REF
= 1.1V) inputs
3.
Combining input standards and output standards.
Input standards and output standards with the same
input V
CCO
and output V
CCO
requirement can be
combined in the same bank.
Compatible example:
LVDS_25 output and HSTL_I input
Incompatible example:
LVDS_25 output (output V
CCO
= 2.5V) and
HSTL_I_DCI_18 input (input V
CCO
= 1.8V)
4.
Combining bidirectional standards with input or
output standards.
When combining bidirectional I/O
with other standards, make sure the bidirectional
standard can meet rules 1 through 3 above.
5.
Additional rules for combining DCI I/O standards.
a.
No more than one Single Termination type (input or
output) is allowed in the same bank.
Incompatible example:
HSTL_IV_DCI input and HSTL_III_DCI input
b.
No more than one Split Termination type (input or
output) is allowed in the same bank.
Figure 8:
Virtex-II I/O Banks: Top View for Wire-Bond
Packages (CS, FG, & BG)
Figure 9:
Virtex-II I/O Banks: Top View for Flip-Chip
Packages (FF & BF)
ug002_c2_014_112900
Bank 0
Bank 1
Bank 5
Bank 4
B
B
B
B
ds031_66_112900
Bank 1
Bank 0
Bank 4
Bank 5
B
B
B
B
ds122_1_1.fm Page 12 Wednesday, January 7, 2004 9:15 PM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XQ2V1000-4BG575N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4BG728M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4BG728N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4CF1144M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4CF1144N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ2V1000-4BG575N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4BG728M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4BG728N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4CF1144M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V1000-4CF1144N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。