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參數(shù)資料
| 型號： | XQ1701LSO20M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| 中文描述： | QPro系列配置PROM的（學琴），包括抗輻射系列（XQR） |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 99K |
| 代理商： | XQ1701LSO20M |
R
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and inter-
prets it as preamble, length count etc. Since the FPGA is
the master, it issues the necessary number of CCLK pulses,
up to 16 million (2
24
) and DONE goes High. However, the
FPGA configuration will be completely wrong, with potential
contentions inside the FPGA and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded PROMs provide additional memory. After the last bit
from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See
Figure 2
.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET pin goes
Low, assuming the PROM reset polarity option has been
inverted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of D
IN
.
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PDF描述 |
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| XQ1701LSO20N | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQ1701LSO20V | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQ1701LCC44N | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQR1701LCC44M | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQR1701LCC44N | QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XQ1701LSO20N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQ1701L-SO20N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XQ1701LSO20V | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Series Configuration PROMs (XQ) including Radiation-Hardened Series (XQR) |
| XQ-182-RS | 制造商:LAB FACILITY 功能描述:TYPE K MI 1.5MM X 150MM |
| XQ18V04 | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro XQ18V04 (XQR18V04) QML In-System Programmable Configuration PROMs |
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