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參數(shù)資料
| 型號(hào)： | XPS16550 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | PLB v4.6 based PLB interface |
| 中文描述： | 基于小巴小巴v4.6界面 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | XPS16550 |
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XPS 16550 UART (v1.00a)
DS577 April 18, 2007
Product Specification
www.xilinx.com
9
XPS 16550 UART
Register Definition
XPS 16550 UART
Interface
The internal registers of the XPS 16550 UART are offset from the base address C_BASEADDR.
Additionally, some of the internal registers are accessible only when bit 7 of the Line Control Register
(LCR) is set. The XPS 16550 UART internal register set is described in
Table 4
.
XPS 16550 UART
Register Logic
This section tabulates the internal XPS 16550 UART registers, including their reset values (if any).
Please refer to the National Semiconductor PC16550D UART with FIFOs
data sheet
(June, 1995) for a
more detailed description of the register behavior.
Receiver Buffer Register
This is an 8-bit read register as shown in
Figure 3
. The Receiver Buffer Register contains the last
received character. The bit definitions for the register are shown in
Table 5
. The offset and accessibility
of this register from C_BASEADDR value is as shown in
Table 4
.
Table 4:
XPS 16550 UART
Registers
Register Name
LCR(7)+ C_BASEADDR
+ Address
Access
Receiver Buffer Register (RBR)
0 + C_BASEADDR +
0x1000
Read
Transmitter Holding Register (THR)
0 + C_BASEADDR +
0x1000
Write
Interrupt Enable Register (IER)
0 + C_BASEADDR +
0x1004
Read/Write
Interrupt Identification Register (IIR)
0 + C_BASEADDR +
0x1008
Read
FIFO Control Register (FCR)
(3)
X + C_BASEADDR +
0x1008
Write
FIFO Control Register
(2)
,
(3)
1 + C_BASEADDR +
0x1008
Read
Line Control Register (LCR)
X
(1)
+ C_BASEADDR +
0x100C
Read/Write
Modem Control Register (MCR)
X
(1)
+ C_BASEADDR +
0x1010
Read/Write
Line Status Register (LSR)
X
(1)
+ C_BASEADDR +
0x1014
Read/Write
Modem Status Register (MSR)
X
(1)
+ C_BASEADDR +
0x1018
Read/Write
Scratch Register (SCR)
X
(1)
+ C_BASEADDR +
0x101C
Read/Write
Divisor Latch Register (DLL)
1 + C_BASEADDR +
0x1000
Read/Write
Divisor Latch Register (DLM)
1 + C_BASEADDR +
0x1004
Read/Write
Notes:
1. X denotes a don’t care
2. FIFO Control Register is write only in the National PC16550D
3. 16450 UART mode implementation does not include this register
Figure Top x-ref 3
Figure 3:
Receiver Buffer Register (RBR)
0
2
3
24 25 26 27 2
8
29
3
0
3
1
RBR
Re
s
erved
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