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參數(shù)資料
| 型號(hào)： | XCV812E-8FG556I |
| 廠(chǎng)商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 18/116頁(yè) |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-8FG556I |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
14
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
Figure 13
shows a full master/slave system. In this system,
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The SPROM
RESET pin is driven by INIT, and the CE input is driven by
DONE. There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
The sequence of operations necessary to configure a
Virtex-E FPGA serially appears in
Figure 15
.
Figure 16
shows the timing of master-serial configuration.
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0).
Table 10
shows the timing infor-
mation for
Figure 16
.
Figure 14:
Slave-Serial Mode Programming Switching Characteristics
4 T
CCH
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379_a
Figure 15:
Serial Configuration Flowchart
Apply Power
Set PROGRAM = High
Release INIT
If used to delay
Load a Configuration Bit
High
Low
FPGA makes a final
clearing pass and releases
INIT when finished.
FPGA starts to clear
configuration memory.
ds009_15_111799
Configuration Completed
BiEnd of
Yes
No
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
INIT
Figure 16:
Master-Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1 TDSCK
2
TCKDS
DS022_44_071201
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-8FG560C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG560I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8FG560C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG560I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG676C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG676I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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