參數(shù)資料
型號(hào): XCV812E-8FG404C
廠商: Xilinx, Inc.
英文描述: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述: 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場(chǎng)可編程門陣列
文件頁數(shù): 74/116頁
文件大?。?/td> 1087K
代理商: XCV812E-8FG404C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
20
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
Revision History
The following table shows the revision history for this document.
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
Date
Version
Revision
03/23/00
1.0
Initial Xilinx release.
08/01/00
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
In Table 3 (Module 4),
FG676 Fine-Pitch BGA — XCV405E
, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to
Virtex-E Electrical Characteristics
tables.
Updated speed grade -8 numbers in
Virtex-E Electrical Characteristics
tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of
Absolute Maximum Ratings
(Module 3).
Changed all minimum hold times to –0.4 for
Global Clock Set-Up and Hold for LVTTL
Standard, with DLL
(Module 3).
Revised maximum T
DLLPW
in -6 speed grade for
DLL Timing Parameters
(Module 3).
In
Table 4
,
FG676 Fine-Pitch BGA — XCV405E
, pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in
Virtex-E Switching Characteristics
tables.
Converted data sheet to modularized format. See the
Virtex-E Extended Memory Data
Sheet
section.
Updated values in
Virtex-E Switching Characteristics
tables.
09/19/00
1.2
11/20/00
1.3
04/02/01
1.4
04/19/01
1.5
07/23/01
1.6
Under
Absolute Maximum Ratings
, changed (T
SOL
) to 220
°
C .
Changes made to SSTL symbol names in
IOB Input Switching Characteristics Standard
Adjustments
table.
Removed T
SOL
parameter and added footnote to
Absolute Maximum Ratings
table.
Reworded power supplies footnote to
Absolute Maximum Ratings
table.
07/26/01
1.7
09/18/01
1.8
10/25/01
1.9
Updated the speed grade designations used in data sheets, and added
Table 1
, which
shows the current speed grade
designation for each device.
Updated
Power-On Power Supply Requirements
table.
Updated the XCV405E device speed grade designation to Preliminary in
Table 1
.
Updated
Power-On Power Supply Requirements
table.
Updated footnotes to the
DC Input and Output Levels
and
DLL Clock Tolerance, Jitter,
and Phase Information
tables.
Data sheet designation upgraded from Preliminary to Production.
Removed mention of MIL-M-38510/605 specification.
Added link to xapp158 from the
Power-On Power Supply Requirements
section.
11/09/01
2.0
02/01/02
2.1
07/17/02
2.2
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XCV812E-8FG556I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8FG560C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8FG560I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays