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參數(shù)資料
| 型號： | XCV812E-8BG560I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | FPGA, 4704 CLBS, 254016 GATES, 416 MHz, PBGA560 |
| 封裝： | PLASTIC, BGA-560 |
| 文件頁數(shù)： | 35/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-8BG560I |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
31
R
Fundamentals
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in
Table 18
, each buffer type can
support a variety of voltage requirements.
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
http://www.jedec.org
LVTTL
—
Low-Voltage TTL
The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3 V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3 V output source voltage (V
CCO
), but
does not require the use of a reference voltage (V
REF
) or a
termination voltage (V
TT
).
LVCMOS2
—
Low-Voltage CMOS for 2.5 Volts
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard (JESD
8.-5) used for general purpose 2.5 V applications. This stan-
dard requires a 2.5 V output source voltage (V
CCO
), but
does not require the use of a reference voltage (V
REF
) or a
board termination voltage (V
TT
).
LVCMOS18
—
1.8 V Low Voltage CMOS
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (V
REF
) or a board termination voltage
(V
TT
) is not required.
PCI
—
Peripheral Component Interface
The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (V
REF
) or a board termination voltage (V
TT
), how-
ever, it does require a 3.3 V output source voltage (V
CCO
).
GTL
—
Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox. Xil-
inx has implemented the terminated variation for this stan-
dard. This standard requires a differential amplifier input
buffer and a Open Drain output buffer.
GTL+
—
Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
HSTL
—
High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5 V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
Table 18:
Virtex-E Supported I/O Standards
I/O
Standard
Output
V
CCO
Input
V
CCO
Input
V
REF
Board
Termination
Voltage (V
TT
)
LVTTL
3.3
3.3
N/A
N/A
LVCMOS2
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
SSTL3 I & II
3.3
N/A
1.50
1.50
SSTL2 I & II
2.5
N/A
1.25
1.25
GTL
N/A
N/A
0.80
1.20
GTL+
N/A
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
3.3
N/A
N/A
PCI66_3
3.3
3.3
N/A
N/A
BLVDS & LVDS
2.5
N/A
N/A
N/A
LVPECL
3.3
N/A
N/A
N/A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-8BG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8BG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8FG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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