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參數(shù)資料
| 型號(hào)： | XCV812E-8BG404I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 28/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-8BG404I |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
24
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
Operating Modes
Virtex-E block SelectRAM+ memory supports two operating
modes.
Read Through
Write Back
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on the desire to have a faster clock-to-out
versus set-up time. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the read
pulse clock.
Write Back (one clock edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
1.
All inputs are registered with the port clock and have a
set-up to clock timing specification.
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
The block SelectRAM elements are true SRAM
memories and do not have a combinatorial path from
the address to the output. The LUT SelectRAM+ cells in
the CLBs are still available with this function.
The ports are completely independent from each other
(
i.e.,
clocking, control, address, read/write function, and
data width) without arbitration.
A write operation requires only one clock edge.
A read operation requires only one clock edge.
2.
3.
4.
5.
6.
The output ports are latched with a self-timed circuit to guar-
antee a glitch-free read. The state of the output port does
not change until the port executes another read or write
operation.
Library Primitives
Figure 31
and
Figure 32
show the two generic library block
SelectRAM+ primitives.
Table 14
describes all of the avail-
able primitives for synthesis and simulation.
Figure 31:
Dual-Port Block SelectRAM+ Memory
Figure 32:
Single-Port Block SelectRAM+ Memory
Table 14:
Available Library Primitives
Primitive
Port A Width
Port B Width
RAMB4_S1
RAMB4_S1_S1
RAMB4_S1_S2
RAMB4_S1_S4
RAMB4_S1_S8
RAMB4_S1_S16
1
N/A
1
2
4
8
16
RAMB4_S2
RAMB4_S2_S2
RAMB4_S2_S4
RAMB4_S2_S8
RAMB4_S2_S16
2
N/A
2
4
8
16
RAMB4_S4
RAMB4_S4_S4
RAMB4_S4_S8
RAMB4_S4_S16
4
N/A
4
8
16
RAMB4_S8
RAMB4_S8_S8
RAMB4_S8_S16
8
N/A
8
16
RAMB4_S16
RAMB4_S16_S16
16
N/A
16
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
ds022_032_121399
ds022_033_121399
DO[#:0]
WE
EN
RST
CLK
ADDR[#:0]
DI[#:0]
RAMB4_S#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-8BG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG560C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG560I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG560C | 功能描述:IC FPGA 1.8V C-TEMP 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-8BG560I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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