- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375033 > XCV812E-7FG900I (XILINX INC) Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | XCV812E-7FG900I |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | FPGA, 4704 CLBS, 254016 GATES, 400 MHz, PBGA900 |
| 封裝： | PLASTIC, FBGA-900 |
| 文件頁(yè)數(shù)： | 17/116頁(yè) |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7FG900I |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)當(dāng)前第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
13
R
Table 9
lists the total number of bits required to configure
each device.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
For more information on serial PROMs, see the PROM data
sheet at
http://www.xilinx.com/partinfo/ds026.pdf
.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13
shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected.
Figure 14
shows slave-serial configuration
timing.
Table 10
provides more detail about the characteristics
shown in
Figure 14
. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Table 9:
Virtex-E Bitstream Lengths
Device
# of Configuration Bits
XCV405E
3,430,400
XCV812E
6,519,648
Table 10:
Master/Slave Serial Mode Programming Switching
Description
Figure
References
Symbol
Values
Units
CCLK
DIN setup/hold, slave mode
1/2
T
DCC
/T
CCD
5.0/0.0
ns, min
DIN setup/hold, master mode
1/2
T
DSCK
/T
CKDS
5.0/0.0
ns, min
DOUT
3
T
CCO
12.0
ns, max
High time
4
T
CCH
5.0
ns, min
Low time
5
T
CCL
5.0
ns, min
Maximum Frequency
F
CC
66
MHz, max
Frequency Tolerance, master mode with respect to nominal
+45% –30%
Figure 13:
Master/Slave Serial Mode Circuit Diagram
VIRTEX-E
MASTER
SERIAL
VIRTEX-E,
XC4000XL,
SLAVE
XC1701L
PROGRAM
M2
M0 M1
DOUT
CCLK
DIN
CLK
DATA
CE
RESET/OE
3.3V
CEO
DONE
INIT
INIT
DONE
PROGRAM
PROGRAM
CCLK
DIN
DOUT
M2
M0 M1
(Low Reset Option Used)
4.7 K
XCVE_ds_013
N/C
N/C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-8BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG560C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8BG404C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG556I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG560C | 功能描述:IC FPGA 1.8V C-TEMP 560-MBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。