參數(shù)資料
型號: XCV812E-7FG900C
廠商: XILINX INC
元件分類: FPGA
英文描述: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述: FPGA, 4704 CLBS, 254016 GATES, 400 MHz, PBGA900
封裝: PLASTIC, FBGA-900
文件頁數(shù): 68/116頁
文件大小: 1087K
代理商: XCV812E-7FG900C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
14
www.xilinx.com
1-800-255-7778
DS025-3 (v2.2) July 17, 2002
R
CLB Distributed RAM Switching Characteristics
Description
(1)
Symbol
Speed Grade
Units
Min
-8
-7
-6
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode
T
SHCKO16
0.67
1.38
1.5
1.7
ns, max
Clock CLK to X/Y outputs (WE active) 32 x 1 mode
T
SHCKO32
0.84
1.66
1.9
2.1
ns, max
Shift-Register Mode
Clock CLK to X/Y outputs
T
REG
1.25
2.39
2.9
3.2
ns, max
Setup and Hold Times before/after Clock CLK
F/G address inputs
T
AS
/T
AH
0.19 / 0
0.38 / 0
0.42 / 0
0.47 / 0
ns, min
BX/BY data inputs (DIN)
T
DS
/T
DH
0.44 / 0
0.87 / 0
0.97 / 0
1.09 / 0
ns, min
SR input (WE)
T
WS
/T
WH
0.29 / 0
0.57 / 0
0.7 / 0
0.8 / 0
ns, min
Clock CLK
Minimum Pulse Width, High
T
WPH
0.96
1.9
2.1
2.4
ns, min
Minimum Pulse Width, Low
T
WPL
0.96
1.9
2.1
2.4
ns, min
Minimum clock period to meet address write cycle time
T
WC
1.92
3.8
4.2
4.8
ns, min
Shift-Register Mode
Minimum Pulse Width, High
T
SRPH
1.0
1.9
2.1
2.4
ns, min
Minimum Pulse Width, Low
T
SRPL
1.0
1.9
2.1
2.4
ns, min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
Figure 3:
Dual-Port Block SelectRAM
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
WEA
ENA
RSTA
CLKA
ADDRA[#:0]
DIA[#:0]
DOA[#:0]
DOB[#:0]
RAMB4_S#_S#
ds022_06_121699
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XCV812E-7FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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XCV812E-8BG556C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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