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參數(shù)資料
| 型號： | XCV812E-7FG676C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 71/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7FG676C |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
17
R
Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Set-Up and Hold for LVTTL Standard,
with
DLL
Global Clock Set-Up and Hold for LVTTL Standard,
without
DLL
Description
(1)
Symbol
Device
(3)
Speed Grade
(2)
Units
Min
-8
-7
-6
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time
delay by the values shown in
‘‘IOB Input Switching
Characteristics Standard Adjustments’’ on page 6
.
No Delay
T
PSDLL
/T
PHDLL
XCV405E
1.5 / –0.4
1.5 / –0.4
1.6 / –0.4
1.7 / –0.4
ns
Global Clock and IFF, with DLL
XCV812E
1.5 / –0.4
1.5 / –0.4
1.7 / –0.4
ns
Notes:
1.
2.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
3.
Description
(1)
Symbol
Device
(3)
Speed Grade
(2)
Units
Min
-8
-7
-6
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time delay
by the values shown in
‘‘IOB Input Switching Characteristics
Standard Adjustments’’ on page 6
.
Full Delay
T
PSFD
/T
PHFD
XCV405E
2.3 / 0
2.3 / 0
2.3 / 0
2.3 / 0
ns
Global Clock and IFF, without DLL
XCV812E
2.5 / 0
2.5 / 0
2.5 / 0
2.5 / 0
ns
Notes:
1.
2.
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7FG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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