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參數(shù)資料
| 型號： | XCV812E-7FG676C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 48/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7FG676C |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
44
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
LVDS
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in
Figure 54
. A sample circuit illustrating a
valid termination for receiving LVDS signals appears in
Figure 55
.
Table 38
lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on
Table 40
.
LVPECL
Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination technique for transmitting LVPECL signals
appears in
Figure 56
. A sample circuit illustrating a valid ter-
mination for receiving LVPECL signals appears in
Figure 57
.
Table 39
lists DC voltage specifications. Further
information on the specific termination resistor packs shown
can be found on
Table 40
.
Figure 54:
Transmitting LVDS Signal Circuit
Figure 55:
Receiving LVDS Signal Circuit
Table 38:
LVDS Voltage Specifications
Parameter
Min
Typ
Max
V
CCO
V
ICM(2)
V
OCM(1)
V
IDIFF
(1)
V
ODIFF
(1)
V
OH(1)
V
OL(1)
2.375
2.5
2.625
0.2
1.25
2.2
1.125
1.25
1.375
0.1
0.35
-
0.25
0.35
0.45
1.25
-
-
-
-
1.25
Notes:
1.
2.
Measured with a 100
resistor across Q and Q.
Measured with a differential input voltage =
+
/
350 mV.
x133_19_122799
Q
Z0 = 50
Z0 = 50
Q
Virtex-E
FPGA
to LVDS Receiver
to LVDS Receiver
RDIV
R
S
165
R
S
165
2.5V
V
CCO
= 2.5V
LVDS
Output
DATA
Transmit
1/4 of Bourns
Part Number
CAT16-LV4F12
x133_29_122799
Q
Z0 = 50
LVDS_IN
LVDS_IN
Z0 = 50
RT
Q
DATA
Receive
from
LVDS
Driver
VIRTEX-E
FPGA
+
–
Figure 56:
Transmitting LVPECL Signal Circuit
Figure 57:
Receiving LVPECL Signal Circuit
Table 39:
LVPECL Voltage Specifications
Parameter
Min
Typ
Max
V
CCO
3.0
3.3
3.6
V
REF
-
-
-
V
TT
-
-
-
V
IH
1.49
-
2.72
V
IL
0.86
-
2.125
V
OH
1.8
-
-
V
OL
-
-
1.57
Note: For more detailed information, see
LVPECL DC
Specifications
x133_20_122799
Q
Z0 = 50
LVPECL_OUT
LVPECL_OUT
Z0 = 50
Q
Virtex-E
FPGA
to LVPECL Receiver
to LVPECL Receiver
RDIV
187
R
S
100
R
S
100
3.3V
DATA
Transmit
1/4 of Bourns
Part Number
CAT16-PC4F12
x133_21_122799
Q
Z0 = 50
LVPECL_IN
LVPECL_IN
Z0 = 50
RT
Q
DATA
Receive
from
LVPECL
Driver
VIRTEX-E
FPGA
+
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7FG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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