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| 型號(hào)： | XCV812E-7FG560C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 43/116頁(yè) |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7FG560C |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
39
R
Application Examples
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
Termination Examples
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
GTL
A sample circuit illustrating a valid termination technique for
GTL is shown in
Figure 44
.
Table 23
lists DC voltage speci-
fications.
GTL+
A sample circuit illustrating a valid termination technique for
GTL+ appears in
Figure 45
. DC voltage specifications
appear in
Table 24
.
Figure 44:
Terminated GTL
V
REF
= 0.8V
V
TT
= 1.2V
50
50
V
CCO
= N/A
Z = 50
GTL
x133_08_111699
V
TT
= 1.2V
Table 23:
GTL Voltage Specifications
Parameter
Min
Typ
Max
V
CCO
V
REF
= N
×
V
TT1
V
TT
V
IH
= V
REF
+ 0.05
V
IL
= V
REF
– 0.05
V
OH
V
OL
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA) at 0.4V
I
OL
at V
OL
(mA) at 0.2V
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
-
N/A
-
0.74
0.8
0.86
1.14
1.2
1.26
0.79
0.85
-
-
0.75
0.81
-
-
-
-
0.2
0.4
-
-
-
32
-
-
-
-
40
Figure 45:
Terminated GTL+
Table 24:
GTL+ Voltage Specifications
Parameter
Min
Typ
Max
V
CCO
V
REF
= N
×
V
TT1
V
TT
V
IH
= V
REF
+ 0.1
V
IL
= V
REF
– 0.1
V
OH
V
OL
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA) at 0.6V
I
OL
at V
OL
(mA) at 0.3V
Note: N must be greater than or equal to 0.653 and less than
or equal to 0.68.
-
-
-
0.88
1.0
1.12
1.35
1.5
1.65
0.98
1.1
-
-
0.9
1.02
-
-
-
0.3
0.45
0.6
-
-
-
36
-
-
-
-
48
V
REF
= 1.0V
V
TT
= 1.5V
50
V
CCO
= N/A
Z = 50
GTL+
x133_09_012400
50
V
TT
= 1.5V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7FG560I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7FG560I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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