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參數(shù)資料
| 型號(hào)： | XCV812E-7FG560C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 17/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7FG560C |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
13
R
Table 9
lists the total number of bits required to configure
each device.
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
For more information on serial PROMs, see the PROM data
sheet at
http://www.xilinx.com/partinfo/ds026.pdf
.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed to the DOUT pin.
Data on the DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13
shows a full master/slave system. A Virtex-E
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011>
to the mode pins (M2, M1, M0). A weak pull-up on the mode
pins makes slave-serial the default mode if the pins are left
unconnected.
Figure 14
shows slave-serial configuration
timing.
Table 10
provides more detail about the characteristics
shown in
Figure 14
. Configuration must be delayed until the
INIT pins of all daisy-chained FPGAs are High.
Table 9:
Virtex-E Bitstream Lengths
Device
# of Configuration Bits
XCV405E
3,430,400
XCV812E
6,519,648
Table 10:
Master/Slave Serial Mode Programming Switching
Description
Figure
References
Symbol
Values
Units
CCLK
DIN setup/hold, slave mode
1/2
T
DCC
/T
CCD
5.0/0.0
ns, min
DIN setup/hold, master mode
1/2
T
DSCK
/T
CKDS
5.0/0.0
ns, min
DOUT
3
T
CCO
12.0
ns, max
High time
4
T
CCH
5.0
ns, min
Low time
5
T
CCL
5.0
ns, min
Maximum Frequency
F
CC
66
MHz, max
Frequency Tolerance, master mode with respect to nominal
+45% –30%
Figure 13:
Master/Slave Serial Mode Circuit Diagram
VIRTEX-E
MASTER
SERIAL
VIRTEX-E,
XC4000XL,
SLAVE
XC1701L
PROGRAM
M2
M0 M1
DOUT
CCLK
DIN
CLK
DATA
CE
RESET/OE
3.3V
CEO
DONE
INIT
INIT
DONE
PROGRAM
PROGRAM
CCLK
DIN
DOUT
M2
M0 M1
(Low Reset Option Used)
4.7 K
XCVE_ds_013
N/C
N/C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7FG560I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7FG560I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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