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參數(shù)資料
| 型號(hào)： | XCV812E-7BG900C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 20/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-7BG900C |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
16
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
A flowchart for the write operation appears in
Figure 18
.
Note that if CCLK is slower than f
CCNH
, the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
Figure 19
.
Figure 17:
Write Operations
DS022_45_071702
CCLK
No Write
Write
No Write
Write
DATA[0:7]
CS
WRITE
3
5
BUSY
4
6
7
1
2
Figure 18:
SelectMAP Flowchart for Write Operations
Apply Power
Set PROGRAM = High
Release INIT
If used to delay
On first FPGA
Set WRITE = Low
Enter Data Source
Set CS = Low
On first FPGA
Set CS = High
Apply Configuration Byte
INIT
High
Low
Busy
Low
High
Disable Data Source
Set WRITE = High
andare releasWhen all DONE pins
If no errors,
later FPGAs entreleasing DONE.
first FPGAs entreleasing DONE.
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
clearinFPGA makes a final
INIT when finished.
FPGA starts to clear
configuration memory.
For any other FPGAs
ds009_18_111799
Repeat Sequence A
Configuration Completed
Sequence A
End of Data
Yes
No
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-7BG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7BG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7FG556I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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