參數(shù)資料
型號(hào)： XCV812E-7BG560C
廠商： XILINX INC
元件分類： FPGA
英文描述： Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述： FPGA, 4704 CLBS, 254016 GATES, 400 MHz, PBGA560
封裝： PLASTIC, BGA-560
文件頁數(shù)： 57/116頁
文件大?。?/td> 1087K
代理商： XCV812E-7BG560C
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
3
R
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at minimum V
CCO
with the respective V
OL
and
V
OH
voltage levels shown. Other standards are sample tested.
Input/Output
Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, min
V, max
V, min
V, max
V, Max
V, Min
mA
mA
LVTTL
(1)
– 0.5
0.8
2.0
3.6
0.4
2.4
24
– 24
LVCMOS2
– 0.5
0.7
1.7
2.7
0.4
1.9
12
– 12
LVCMOS18
– 0.5
20% V
CCO
70% V
CCO
1.95
0.4
V
CCO
– 0.4
8
– 8
PCI, 3.3 V
– 0.5
30% V
CCO
50% V
CCO
V
CCO
+ 0.5
10% V
CCO
90% V
CCO
Note 2
Note 2
GTL
– 0.5
V
REF
– 0.05
V
REF
+ 0.05
3.6
0.4
n/a
40
n/a
GTL+
– 0.5
V
REF
– 0.1
V
REF
+ 0.1
3.6
0.6
n/a
36
n/a
HSTL I
(3)
– 0.5
V
REF
– 0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
– 0.4
8
–8
HSTL III
– 0.5
V
REF
– 0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
– 0.4
24
–8
HSTL IV
– 0.5
V
REF
– 0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
– 0.4
48
–8
SSTL3 I
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
V
REF
– 0.6
V
REF
+ 0.6
8
–8
SSTL3 II
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
V
REF
– 0.8
V
REF
+ 0.8
16
–16
SSTL2 I
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
V
REF
– 0.61
V
REF
+ 0.61
7.6
–7.6
SSTL2 II
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
V
REF
– 0.80
V
REF
+ 0.80
15.2
–15.2
CTT
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
V
REF
– 0.4
V
REF
+ 0.4
8
–8
AGP
– 0.5
V
REF
– 0.2
V
REF
+ 0.2
3.6
10% V
CCO
90% V
CCO
Note 2
Note 2
Notes:
1.
2.
3.
V
OL
and V
OH
for lower drive currents are sample tested.
Tested according to the relevant specifications.
DC input and output levels for HSTL18 (HSTL I/O standard with V
CCO
of 1.8 V) are provided in an
HSTL white paper
on the Xilinx
website.
相關(guān)PDF資料
PDF描述
XCV812E-7BG560I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900C Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900I Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV812E-7BG560I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-7BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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