- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375033 > XCV812E-6FG900C (XILINX INC) Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | XCV812E-6FG900C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | FPGA, 4704 CLBS, 254016 GATES, 357 MHz, PBGA900 |
| 封裝： | PLASTIC, FBGA-900 |
| 文件頁數(shù)： | 20/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-6FG900C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
16
www.xilinx.com
1-800-255-7778
DS025-2 (v2.1) July 17, 2002
R
A flowchart for the write operation appears in
Figure 18
.
Note that if CCLK is slower than f
CCNH
, the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
Figure 19
.
Figure 17:
Write Operations
DS022_45_071702
CCLK
No Write
Write
No Write
Write
DATA[0:7]
CS
WRITE
3
5
BUSY
4
6
7
1
2
Figure 18:
SelectMAP Flowchart for Write Operations
Apply Power
Set PROGRAM = High
Release INIT
If used to delay
On first FPGA
Set WRITE = Low
Enter Data Source
Set CS = Low
On first FPGA
Set CS = High
Apply Configuration Byte
INIT
High
Low
Busy
Low
High
Disable Data Source
Set WRITE = High
andare releasWhen all DONE pins
If no errors,
later FPGAs entreleasing DONE.
first FPGAs entreleasing DONE.
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
clearinFPGA makes a final
INIT when finished.
FPGA starts to clear
configuration memory.
For any other FPGAs
ds009_18_111799
Repeat Sequence A
Configuration Completed
Sequence A
End of Data
Yes
No
相關PDF資料 |
PDF描述 |
|---|---|
| XCV812E-6FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復。