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參數(shù)資料
| 型號： | XCV812E-6FG676I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴(kuò)展1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 73/116頁 |
| 文件大?。?/td> | 1087K |
| 代理商： | XCV812E-6FG676I |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.2) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 3 of 4
19
R
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF
CLKDLL
Units
Description
Symbol
F
CLKIN
Min
Max
Min
Max
Input Clock Period Tolerance
T
IPTOL
-
1.0
-
1.0
ns
Input Clock Jitter Tolerance (Cycle to Cycle)
T
IJITCC
-
±
150
-
±
300
ps
Time Required for DLL to Acquire Lock
(6)
T
LOCK
> 60 MHz
-
20
-
20
μ
s
50 - 60 MHz
-
-
-
25
μ
s
40 - 50 MHz
-
-
-
50
μ
s
30 - 40 MHz
-
-
-
90
μ
s
25 - 30 MHz
-
-
-
120
μ
s
Output Jitter (cycle-to-cycle) for any DLL Clock Output
(1)
T
OJITCC
±
60
±
60
ps
Phase Offset between CLKIN and CLKO
(2)
T
PHIO
±
100
±
100
ps
Phase Offset between Clock Outputs on the DLL
(3)
T
PHOO
±
140
±
140
ps
Maximum Phase Difference between CLKIN and CLKO
(4)
T
PHIOM
±
160
±
160
ps
Maximum Phase Difference between Clock Outputs on the DLL
(5)
T
PHOOM
±
200
±
200
ps
Notes:
1.
Output Jitter
is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution,
excluding
input clock jitter.
Phase Offset between CLKIN and CLKO
is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding
Output Jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL
is the worst-case fixed time difference between rising edges of any two DLL
outputs,
excluding
Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO
is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (
excluding
input clock jitter).
Maximum Phase DIfference between Clock Outputs on the DLL
is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (
excluding
input clock jitter).
Add 30% to the value for Industrial grade parts.
2.
3.
4.
5.
6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV812E-6FG900C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG900I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-6FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV812E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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