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參數(shù)資料
| 型號： | XCV812E-6FG404I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | 的Virtex娥內(nèi)存擴展1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 21/116頁 |
| 文件大小： | 1087K |
| 代理商： | XCV812E-6FG404I |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v2.1) July 17, 2002
www.xilinx.com
1-800-255-7778
Module 2 of 4
17
R
Boundary-Scan Mode
In the boundary-scan mode, no non-dedicated pins are
required, configuration being done entirely through the
IEEE 1149.1 Test Access Port.
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
1.
Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2.
Enter the Shift-DR (SDR) state
3.
Shift a configuration bitstream into TDI
4.
Return to Run-Test-Idle (RTI)
5.
Load the JSTART instruction into IR
6.
Enter the SDR state
7.
8.
Clock TCK through the startup sequence
Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0).
Configuration Sequence
The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
The power-up timing of configuration signals is shown in
Figure 20
.
Figure 19:
SelectMAP Write Abort Waveforms
CCLK
CS
WRITE
Abort
DATA[0:7]
BUSY
DS022_46_071702
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| XCV812E-6FG556C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG556I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG560C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG560I | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG676C | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-6FG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG556I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG560C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG560I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-6FG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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