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參數(shù)資料
| 型號： | XCV50E-6FG240C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| 中文描述： | 的Virtex⑩娥1.8伏現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 87K |
| 代理商： | XCV50E-6FG240C |
Virtex
-E 1.8 V Field Programmable Gate Arrays
R
DS022-1 (v2.2) November 9, 2001
Preliminary Product Specification
1-800-255-7778Module 1 of 4
3
resources. The abundance of routing resources permits the
Virtex-E family to accommodate even the largest and most
complex designs.
Virtex-E FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. Con-
figuration data can be read from an external SPROM (mas-
ter serial mode), or can be written into the FPGA
(SelectMAP
, slave serial, and JTAG modes).
The standard Xilinx Foundation Series
and Alliance
Series
Development systems deliver complete design
support for Virtex-E, covering every aspect from behavioral
and schematic entry, through simulation, automatic design
translation and implementation, to the creation and down-
loading of a configuration bit stream.
Higher Performance
Virtex-E devices provide better performance than previous
generations of FPGAs. Designs can achieve synchronous
system clock rates up to 240 MHz including I/O or 622 Mb/s
using Source Synchronous data transmission architech-
tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica-
tions, and interfaces can be implemented that operate at
33 MHz or 66 MHz.
While performance is design-dependent, many designs
operate internally at speeds in excess of 133 MHz and can
achieve over 311 MHz.
Table 2
shows performance data for
representative circuits, using worst-case timing parameters.
Virtex-E Device/Package Combinations and Maximum I/O
Table 2:
Performance for Common Circuit Functions
Function
Bits
Virtex-E (-7)
Register-to-Register
Adder
16
64
4.3 ns
6.3 ns
Pipelined Multiplier
8 x 8
16 x 16
4.4 ns
5.1 ns
Address Decoder
16
64
3.8 ns
5.5 ns
16:1 Multiplexer
4.6 ns
Parity Tree
9
18
36
3.5 ns
4.3 ns
5.9 ns
Chip-to-Chip
HSTL Class IV
LVTTL,16mA, fast slew
LVDS
LVPECL
Table 3:
Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV
50E
XCV
100E
XCV
200E
XCV
300E
XCV
400E
XCV
600E
XCV
1000E
XCV
1600E
XCV
2000E
XCV
2600E
XCV
3200E
CS144
94
94
94
PQ240
158
158
158
158
158
HQ240
158
158
BG352
196
260
260
BG432
316
316
316
BG560
404
404
404
404
404
FG256
176
176
176
176
FG456
284
312
FG676
404
444
FG680
512
512
512
512
FG860
660
660
660
FG900
512
660
700
FG1156
660
724
804
804
804
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV50E-7BG240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV50E-7FG240C | AB 10C 10#16 SKT ANG PLG ROHS RoHS Compliant: Yes |
| XCV50E-7HQ240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV50E-8BG240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-6FG240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV50E-6FG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV50E6FG256C | 制造商:Xilinx 功能描述: |
| XCV50E-6FG256C | 功能描述:IC FPGA 1.8V C-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XCV50E-6FG256C0773 | 制造商:Xilinx 功能描述: |
| XCV50E-6FG256I | 功能描述:IC FPGA 1.8V I-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
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