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參數資料
| 型號： | XCV300E-8PQ240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | FPGA, 1536 CLBS, 82944 GATES, 416 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數： | 4/5頁 |
| 文件大?。?/td> | 87K |
| 代理商： | XCV300E-8PQ240I |
Virtex-E Ordering Information
Revision History
The following table shows the revision history for this document.
Figure 1:
Ordering Information
Date
Version
Revision
12/7/99
1.0
Initial Xilinx release.
1/10/00
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
BYP
values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
1.3
Updated pinout tables, V
CC
page 20, and corrected Figure 20.
5/23/00
1.4
Correction to table on p. 22.
7/10/00
1.5
Numerous minor edits.
Data sheet upgraded to Preliminary.
Preview -8 numbers added to
Virtex-E Electrical Characteristics
tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade
values in tables on pages 35-37.
Min values added to
Virtex-E Electrical Characteristics
tables.
XCV2600E and XCV3200E numbers added to
Virtex-E Electrical Characteristics
tables (Module 3).
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to
“
No Connect in the XCV100E
“
and removed duplicate V
CCINT
pins in Table ~ (Module 4).
Changed pin J10 to
“
No connect in XCV600E
”
in Table 74 (Module 4).
Changed pin J30 to
“
VREF option only in the XCV600E
”
in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be
“
AO in the XCV1000E, XCV1600E
“
.
8/1/00
1.6
9/20/00
1.7
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
Speed Grade
(-6, -7, -8)
DS022_043_072000
相關PDF資料 |
PDF描述 |
|---|---|
| XCV300E-8TQ144C | Field Programmable Gate Arrays |
| XCV300E-8TQ144I | Field Programmable Gate Arrays |
| XCV50E-6FG240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV50E-7BG240C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV50E-7FG240C | AB 10C 10#16 SKT ANG PLG ROHS RoHS Compliant: Yes |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XCV300E-8PQG240C | 制造商:Xilinx 功能描述:FPGA VIRTEX-E 82.944K GATES 6912 CELLS 416MHZ 0.18UM 1.8V 24 - Trays |
| XCV300E-8TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV300E-8TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV3200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC17V00 Series Configuration PROMs |
| XCV3200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
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