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參數資料
| 型號： | XCV100E-6PQ240C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Virtex-E 1.8 V Field Programmable Gate Arrays |
| 中文描述： | FPGA, 600 CLBS, 32400 GATES, 357 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數： | 4/5頁 |
| 文件大?。?/td> | 87K |
| 代理商： | XCV100E-6PQ240C |
Virtex-E Ordering Information
Revision History
The following table shows the revision history for this document.
Figure 1:
Ordering Information
Date
Version
Revision
12/7/99
1.0
Initial Xilinx release.
1/10/00
1.1
Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL,
Select RAM and SelectI/O information.
1/28/00
1.2
Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54,
& 55, text explaining Table 5, T
BYP
values, buffered Hex Line info, p. 8, I/O Timing
Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote
references.
2/29/00
1.3
Updated pinout tables, V
CC
page 20, and corrected Figure 20.
5/23/00
1.4
Correction to table on p. 22.
7/10/00
1.5
Numerous minor edits.
Data sheet upgraded to Preliminary.
Preview -8 numbers added to
Virtex-E Electrical Characteristics
tables.
Reformatted entire document to follow new style guidelines.
Changed speed grade
values in tables on pages 35-37.
Min values added to
Virtex-E Electrical Characteristics
tables.
XCV2600E and XCV3200E numbers added to
Virtex-E Electrical Characteristics
tables (Module 3).
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to
“
No Connect in the XCV100E
“
and removed duplicate V
CCINT
pins in Table ~ (Module 4).
Changed pin J10 to
“
No connect in XCV600E
”
in Table 74 (Module 4).
Changed pin J30 to
“
VREF option only in the XCV600E
”
in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be
“
AO in the XCV1000E, XCV1600E
“
.
8/1/00
1.6
9/20/00
1.7
Example: XCV300E-6PQ240C
Device Type
Temperature Range
C = Commercial (Tj = 0 C to +85 C)
I = Industrial (Tj = -40 C to +100 C)
Number of Pins
Package Type
BG = Ball Grid Array
FG = Fine Pitch Ball Grid Array
HQ = High Heat Dissipation
Speed Grade
(-6, -7, -8)
DS022_043_072000
相關PDF資料 |
PDF描述 |
|---|---|
| XCV100E-6PQ240I | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-7BG240I | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-7BG352C | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-7BG352I | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-7CS144C | Virtex-E 1.8 V Field Programmable Gate Arrays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XCV100E-6PQ240C0773 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XCV100E-6PQ240I | 功能描述:IC FPGA 1.8V I-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Virtex®-E 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV100E-6PQG240C | 功能描述:IC FPGA 1.8V 128K GATES 240-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Virtex®-E 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數:3411 邏輯元件/單元數:43661 RAM 位總計:2138112 輸入/輸出數:358 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XCV100E-7BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-7BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
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