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參數(shù)資料
| 型號： | XCR3384XL-10PQ208I |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 384 Macrocell CPLD |
| 中文描述： | EE PLD, 10 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 94K |
| 代理商： | XCR3384XL-10PQ208I |
XCR3384XL: 384 Macrocell CPLD
DS024 (v1.3) August 10, 2001
Advance Product Specification
1-800-255-77783
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol
T
PD1
T
PD2
T
CO
T
SUF(4)
T
SU(4)
T
H(4)
T
WLH(4)
Tt
PLH(4)
T
R(4)
T
L(4)
f
SYSTEM(4)
T
CONFIG(4)
T
INIT(4)
T
POE(4)
T
POD(4)
T
PCO(4)
T
PAO(4)
Notes:
1.
Specifications measured with one output switching.
2.
See XPLA3 family data sheet (DS012) for recommended operating conditions.
3.
See
Figure 4
for derating.
4.
These parameters guaranteed by design and/or characterization, not testing.
5.
Typical current draw during configuration is 10 mA at 3.6V.
6.
Output C
L
= 5 pF.
Parameter
-7
-10
-12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
μ
s
μ
s
ns
ns
ns
ns
Min.
-
-
-
2.5
4.8
0
3.0
4.5
-
-
-
-
-
-
-
-
-
Max.
7.0
7.5
4.5
-
-
-
-
-
20
20
127
TBD
TBD
9.0
9.0
8.0
9.0
Min.
-
-
-
3.0
6.5
0
4.0
6.0
-
-
-
-
-
-
-
-
-
Max.
9.0
10.0
5.8
-
-
-
-
-
20
20
102
TBD
TBD
11.0
11.0
10.3
11.0
Min.
-
-
-
3.0
7.9
0
5.0
7.5
-
-
-
-
-
-
-
-
-
Max.
10.8
12.0
6.9
-
-
-
-
-
20
20
83
TBD
TBD
13.0
13.0
12.4
13.0
Propagation delay time (single p-term)
Propagation delay time (OR array)
(3)
Clock to output (global synchronous pin clock)
Setup time fast
Setup time
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
Input fall time
Maximum system frequency
Configuration time
(5)
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
(6)
P-term clock to output
P-term set/reset to output valid
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| XCR3384XL-10PQG208C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 9K GATES 384 MCRCLLS 125MHZ COMM 0.35U - Trays |
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| XCR3384XL-10TQ144IES | 制造商:Xilinx 功能描述: |
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