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XCR3320: 320 Macrocell SRAM CPLD
DS033 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
6
This product has been discontinued. Please see
for details.Simple Timing Model
Figure 5
shows the XCR3320 timing model. The XCR3320
timing model is very simple compared to the models of
competing architectures. There are three main timing
parameters: the pin-to-pin delay for combinatorial logic
functions (t
PD
), the input pin to register set up time (t
SU
),
and the register clock to valid output time (t
CO
). As the
model shows, timing is only dependent on whether or not
the PLA array is used, and whether or not the logic function
is created within a single Fast Module or uses the GZIA.
The timing starts with a set time for t
PD
and t
SU
through the
PAL array in a Fast Module, and there are fixed delays
added for use of the PLA array or the GZIA. The t
CO
(pin-to-pin) timing specification never changes. For exam-
ple, a combinatorial logic function of four or fewer product
terms constructed from inputs within the same logic block
would have a t
PD
delay of 7.5 ns. If the logic function were
more than four product terms wide, the delay would be t
PD
plus the fixed PLA delay, or 7.5 +1.5 = 9.0 ns. A function
that used the PAL array and inputs from a different Fast
Module would have a propagation delay of t
PD
plus the
fixed GZIA delay, or 7.5 + 2.0 = 9.5 ns.
Figure 5: XCR3320 Timing Module
OUTPUT PIN
INPUT PIN
t
PD_PAL
= COMBINATORIAL PAL
t
PD_PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL
t
SU_PLA
REGISTERED
t
CO
Within a Fast Module:
Using the Global ZIA:
OUTPUT PIN
INPUT PIN
t
PD_PAL
= COMBINATORIAL PAL + GZD
t
PD_PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL + GZD
t
SU_PLA
REGISTERED
t
CO
SP00591B
GLOBAL CLOCK PIN
GLOBAL CLOCK PIN