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參數(shù)資料
| 型號： | XCR3320 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 320 Macrocell SRAM CPLD(320宏單元靜態(tài)RAM復(fù)雜可編程邏輯器件) |
| 中文描述： | 320宏單元CPLD實現(xiàn)的SRAM（320宏單元靜態(tài)RAM的復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 41/43頁 |
| 文件大?。?/td> | 392K |
| 代理商： | XCR3320 |
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R
XCR3320: 320 Macrocell SRAM CPLD
41
www.xilinx.com
1-800-255-7778
DS033 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.160 Pin Description Table
Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.
Table 18: Pin Function Description
Symbol
V
CC
Pin Number
15, 23, 40, 53,
62, 71, 80, 81,
99, 106, 121,
130, 139, 148
8, 17, 24, 32,
47, 60, 64, 77,
89, 98, 104,
113, 124, 137,
141, 154
159
Type
-
Description
Positive power supply.
GND
-
Ground supply.
resetn
I
During configuration,
resetn
forces the start of initialization. After configuration,
resetn is a direct input which can be used to asynchronously reset all the flip-flops. If
the global reset is not being used, this pin should be pulled High. If the rise time of
the prgmn signal is greater than 1
μ
s, this signal must be held low until prgmn is High.
In the master modes,
cclk
is an output which strobes configuration data in. In the
slave or synchronous peripheral mode, cclk is an input synchronous with the data on
din or D[7:0]. After configuration, this pin should be pulled Low.
done
is a bi-directional signal with a weak pull-up resistor attached. As an output,
done pulling High indicates configuration is complete. As an input, a Low level on
done will delay the enabling of user I/O. If only one device is used, this pin can be left
floating. If multiple devices are daisy chained, an external pull-up should be used.
prgmn
is an active-low input that forces the restart of configuration and initialization
and resets the boundary-scan circuitry. After configuration, the pin should be pulled
high. This signal must have a rise time less than 1 microsecond. If the rise time of this
signal is greater than 1 microsecond, resetn must be held low until prgmn is high.
Special purpose configuration pin that must be left floating during configuration for all
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
“
Terminations
”
on page 8
for more information.
Special purpose configuration pin that must be left floating during configuration for all
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
“
Terminations
”
on page 8
for more information.
During slave serial or master serial configuration modes,
din
accepts serial
configuration data synchronous with cclk. During parallel configuration modes, din is
the D[0] input. After configuration, the pin is a user-programmable I/O, and no
external termination is required. See the section on terminations for more information.
M2/M1/M0
are used to select the configuration mode. After configuration, the pins are
user-programmable I/O, and no external termination is required. See
“
Terminations
”
on page 8
for more information.
cclk
157
I/O
done
158
I/O
prgmn
160
I
spmi
46
O
mpmi
63
O
din
5
I
M2
M0
M1
M3
95
110
108
151
I
I
M3
should be pulled high during configuration for all configuration modes. After
configuration, the pin is a user-programmable I/O, and no external termination is
required. See
“
Terminations
”
on page 8
for more information.
Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset
are
dedicated pins for boundary-scan through the JTAG port. If JTAG is not being used,
tdi, tck, tms, and trstn should be terminated with a weak pull-up resistor. tdo can be
left unterminated. See
“
Terminations
”
on page 8
for more information.
tdi
tdo
tck
tms
trstn
42
44
41
43
97
I
O
I
I
I
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