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參數(shù)資料
| 型號： | XCR3320 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 320 Macrocell SRAM CPLD(320宏單元靜態(tài)RAM復(fù)雜可編程邏輯器件) |
| 中文描述： | 320宏單元CPLD實現(xiàn)的SRAM（320宏單元靜態(tài)RAM的復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 16/43頁 |
| 文件大小： | 392K |
| 代理商： | XCR3320 |
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R
XCR3320: 320 Macrocell SRAM CPLD
DS033 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
16
This product has been discontinued. Please see
for details.Reconfiguration
To reconfigure the XCR3320 when the device is operating
in the system, a low pulse is input into prgmn. The I/Os not
used for configuration are 3-stated. The XCR3320 then
samples the mode select inputs and begins re-configura-
tion. The mode pins are continuously sampled, so the sig-
nals must be stable while prgmn is low. When configuration
is compete, done is released, allowing it to be pulled high.
CRC Error Checking
CRC checking is done on each frame if enabled by setting
the CRCen bit in the header. If there is an error, a CRC
error is flagged by pulling crcerrn low. The XCR3320 is
forced into the initialization state, and then moves into the
configuration state after prgmn and resetn go high. The
XCR3320 will also pull crcerrn low if an invalid preamble is
detected within a configuration data packet.
XCR3320 Configuration Modes
The method for configuring the XCR3320 is selected by the
m0, m1, and m2 inputs. The m3 input should be high for all
modes. In master modes, cclk is an output with a nominal
frequency of 1 MHz. In slave modes, cclk is an input with a
maximum frequency of 10 MHz if configuring only a single
device, and 1 MHz if devices are daisy chained.
Master Serial Mode
In the master serial mode, the XCR3320 loads the configu-
ration data from an external serial ROM. The configuration
data is either loaded automatically at start-up or on a com-
mand to reconfigure. Serial EEPROMs from Altera, Atmel,
Lucent, Microchip, and Xilinx can be used to configure the
XCR3320 in the master serial mode. This provides a simple
four-pin interface in an eight-pin package. Serial
EEPROMs are available in 32K, 64K, 128K, 256K, and 1M
bit densities.
Configuration in the master serial mode can be done at
power-up and/or upon a configure command. The system
or the XCR3320 must activate the serial EEPROM
’
s
RESET/OE and CE inputs. At power-up, the XCR3320 and
serial EEPROM each contain internal power-on reset cir-
cuitry which allows the XCR3320 to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial EEPROMs
’
internal
address pointer to be reset. After power-up, the XCR3320
automatically enters its initialization phase.
The serial EEPROM/XCR3320 interface used depends on
such factors as the availability of a system reset pulse,
availability of an intelligent host to generate a configure
command, whether a single serial EEPROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
EEPROM contains a single or multiple configuration pro-
grams, etc.
Data is read into the XCR3320 sequentially from the serial
ROM. The DATA output from the serial EEPROM is con-
nected directly into the din input of the XCR3320. The cclk
output from the XCR3320 is connected to the CLOCK input
of the serial EEPROM. During the configuration process,
cclk clocks one data bit into the XCR3320 on each rising
edge.
Since the data and clock are direct connects, the
XCR3320/serial EEPROM interface task is to use the sys-
tem or XCR3320 to enable the RESET/OE and CE of the
serial EEPROM(s). The serial EEPROM
’
s RESET/OE is
programmable to function with RESET active-low and OE
active-high, which allows hdc from the XCR3320 to control
this function.
Likewise, the serial EEPROM could be programmed to
function with RESET active high and OE active low, allow-
ing the ldcn pin from the XCR3320 to control this function.
The XCR3320 done pin is connected to the serial
EEPROM CE to enable the EEPROMs during configuration
and disable them when configuration is complete.
In
Figure 17
, the serial EEPROMs RESET/OE pin has
been programmed to function with RESET active low and
OE active high, and it is controlled by the XCR3320
’
s hdc
pin. This resets the serial EEPROMs during the initializa-
tion state and enables their output during the configuration
state. If a bit error is found during configuration, hdc will go
low, signifying the XCR3320 is back in initialization state
and also resetting the EEPROMs. This restarts the config-
uration process.
The XCR3320 done pin is routed to the CE pin of the
EEPROMs. The Low signal on done during configuration
enable the serial EEPROMs. At the completion of configu-
ration, the High on done disables the EEPROMs.
In
Figure 17
, a serial EEPROM is programmed to configure
a XCR3320. When configuration data requirements exceed
the capacity of a single serial EEPROM, multiple serial
EEPROMs can be cascaded to support the configuration of
a single (or multiple) XCR3320(s). After the last bit from the
first serial ROM is read, the serial ROM outputs CEO Low
and 3-states the DATA output. The next serial ROM recog-
nizes the Low on CE input and outputs configuration data
on the DATA output. After configuration is complete, the
XCR3320
’
s done output into CE disables the serial
EEPROMs.
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