參數(shù)資料
型號: XCR3128-15VQ160C
廠商: Xilinx, Inc.
英文描述: XCR3128: 128 Macrocell CPLD
中文描述: XCR3128:128個宏單元CPLD
文件頁數(shù): 2/18頁
文件大?。?/td> 126K
代理商: XCR3128-15VQ160C
R
XCR3128: 128 Macrocell CPLD
DS034 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
2
The XCR3128 CPLD is electrically reprogrammable using
industry standard device programmers from vendors such
as Data I/O, BP Microsystems, SMS, and others. The
XCR3128 also includes an industry-standard, IEEE
1149.1, JTAG interface through which in-system program-
ming (ISP) and reprogramming of the device is supported.
XPLA
Architecture
Figure 1
shows a high level block diagram of a 128 macro-
cell device implementing the XPLA architecture. The XPLA
architecture consists of logic blocks that are interconnected
by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-
tual crosspoint switch. Each logic block is essentially a
36V16 device with 36 inputs from the ZIA and 16 macro-
cells. Each logic block also provides 32 ZIA feedback paths
from the macrocells and I/O pins.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
family unique is what is inside each logic block and the
design technique used to implement these logic blocks.
The contents of the logic block will be described next.
Figure 1: Xilinx XPLA Architecture
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
ZIA
LOGIC
BLOCK
LOGIC
BLOCK
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
LOGIC
BLOCK
LOGIC
BLOCK
I/O
36
16
16
36
16
16
MC0
MC1
MC15
I/O
MC0
MC1
MC15
SP00464
LOGIC
BLOCK
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