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參數(shù)資料
| 型號： | XCB56364FU100 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 8-BIT, 100 MHz, OTHER DSP, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/162頁 |
| 文件大?。?/td> | 2405K |
| 代理商： | XCB56364FU100 |
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Signal/Connection Descriptions
Serial Host Interface
1-10
DSP56364 Advance Information
MOTOROLA
MOSI
Input or
output
Tri-stated
SPI Master-Out-Slave-In
—When the SPI is configured as a master, MOSI is
the master data output line. The MOSI signal is used in conjunction with the
MISO signal for transmitting and receiving serial data. MOSI is the slave data
input line when the SPI is configured as a slave. This signal is a Schmitt-trig-
ger input when configured for the SPI Slave mode.
HA0
Input
Tri-stated
I
2
C Slave Address 0
—This signal uses a Schmitt-trigger input when config-
ured for the I
2
C mode. When configured for I
2
C slave mode, the HA0 signal is
used to form the slave device address. HA0 is ignored when configured for the
I
2
C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
SS
Input
Input
SPI Slave Select
—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the
SPI master mode, this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error condition is flagged. If
SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output
signal in the high-impedance state.
HA2
Input
Input
I
2
C Slave Address 2
—This signal uses a Schmitt-trigger input when config-
ured for the I
2
C mode. When configured for the I
2
C Slave mode, the HA2 sig-
nal is used to form the slave device address. HA2 is ignored in the I
2
C master
mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant
.
HREQ
Input or
Output
Tri-stated
Host Request
—This signal is an active low Schmitt-trigger input when config-
ured for the master mode but an active low output when configured for the
slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the
SHI is ready for the next data word transfer and deasserted at the first clock
pulse of the new data word transfer. When configured for the master mode,
HREQ is an input. When asserted by the external slave device, it will trigger
the start of the data word transfer by the master. After finishing the data word
transfer, the master will await the next assertion of HREQ to proceed to the
next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external
pull-up in this state.
This input is 5 V tole
rant.
Table 1-9 Serial Host Interface Signals (continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCB56364PV100 | 24-Bit Audio Digital Signal Processor |
| XCCACE-TQ144 | System ACE CompactFlash Solution |
| XCCACE-TQ144I | System ACE CompactFlash Solution |
| XCCACE128-I | System ACE CompactFlash Solution |
| XCCACE256-I | System ACE CompactFlash Solution |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCB56364PV100 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| XCBC01 | 制造商:Excelsys Technologies 功能描述:CONF POWER CHASSIS 700W 6 SLOT |
| XCBMV0502 A | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W AMB XENON BCN |
| XCBMV0502 B | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W BLU XENON BCN |
| XCBMV0502 R | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W RED XENON BCN |
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