- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375005 > XCB56364FU100 (MOTOROLA INC) 24-Bit Audio Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | XCB56364FU100 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 8-BIT, 100 MHz, OTHER DSP, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 11/162頁(yè) |
| 文件大小： | 2405K |
| 代理商： | XCB56364FU100 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
MOTOROLA
DSP56364 Advance Information
1-7
1.5.3
External Bus Control
Table 1-7 External Bus Control Signals
Signal Name
Type
State
during
Reset
Signal Description
AA0–AA1/
RAS0
–
RAS1
Output
Tri-stated
Address Attribute or Row Address
Strobe
—When defined as AA, these
signals can be used as chip selects or additional address lines. When
defined as
RAS
, these signals can be used as
RAS
for DRAM interface.
These signals are tri-statable outputs with programmable polarity. These
signals are tri-stated during hardware reset and when the DSP is in the
stop or wait low-power standby mode.
CAS
Output
Tri-stated
Column Address Strobe
—
CAS
is an active-low output used by DRAM
to strobe the column address. This signal is tri-stated during hardware
reset and when the DSP is in the stop or wait low-power standby mode.
RD
Output
Tri-stated
Read Enable
—
RD
is an active-low output that is asserted to read exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
WR
Output
Tri-stated
Write Enable
—
WR
is an active-low output that is asserted to write exter-
nal memory on the data bus. This signal is tri-stated during hardware reset
and when the DSP is in the stop or wait low-power standby mode.
TA
Input
Ignored
Input
Transfer Acknowledge
—If there is no external bus activity, the
TA
input
is ignored. The
TA
input is a data transfer acknowledge (DTACK) function
that can extend an external bus cycle indefinitely. Any number of wait
states (1, 2. . .infinity) may be added to the wait states inserted by the
BCR by keeping
TA
deasserted. In typical operation,
TA
is deasserted at
the start of a bus cycle, is asserted to enable completion of the bus cycle,
and is deasserted before the next bus cycle. The current bus cycle com-
pletes one clock period after
TA
is asserted synchronous to the internal
system clock. The number of wait states is determined by the
TA
input or
by the bus control register (BCR), whichever is longer. The BCR can be
used to set the minimum number of wait states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at
least one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result.
TA
can operate
synchronously or asynchronously, depending on the setting of the TAS bit
in the operating mode register (OMR).
TA
functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCB56364PV100 | 24-Bit Audio Digital Signal Processor |
| XCCACE-TQ144 | System ACE CompactFlash Solution |
| XCCACE-TQ144I | System ACE CompactFlash Solution |
| XCCACE128-I | System ACE CompactFlash Solution |
| XCCACE256-I | System ACE CompactFlash Solution |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCB56364PV100 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| XCBC01 | 制造商:Excelsys Technologies 功能描述:CONF POWER CHASSIS 700W 6 SLOT |
| XCBMV0502 A | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W AMB XENON BCN |
| XCBMV0502 B | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W BLU XENON BCN |
| XCBMV0502 R | 制造商:Lap Electrical Ltd 功能描述:10-100V 2W RED XENON BCN |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。