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參數(shù)資料
| 型號： | XCA56011BU95 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-BIT DVD DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 8-BIT, 95 MHz, OTHER DSP, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 51/82頁 |
| 文件大小： | 318K |
| 代理商： | XCA56011BU95 |
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Preliminary Information
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
2-25
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
PRELIMINARY
Programming the Serial Clock
The Programmed Serial Clock Cycle, t
I
HDM0 and HRS bits of the HCKR (SHI Clock control Register).
2
CCP
, is specified by the value of the HDM5–
The expression for t
2
CCP
is:
t
2
CCP
= [T
C
×
2
×
(HDM[5:0] + 1)
×
(7
×
(1 – HRS) + 1)]
where
–
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-
by-eight prescaler is operational. When HRS is set, the prescaler is
bypassed.
–
MDM5–HDM0 are the Divider Modulus Select bits.
–
A divide ratio from 1 to 64 (HDM5–HDM0 = 0 to $3F) may be selected.
In I
2
C mode, you may select a value for the Programmed Serial Clock Cycle from:
6
×
T
C
(if HDM[5:0] = $02 and HRS = 1)
to
1024
×
T
C
(if HDM[5:0] = $3F and HRS = 0)
The DSP56011 provides an improved I
2
C bus protocol. In addition to supporting the
100 kHz I
2
C bus protocol, the SHI in I
2
C mode supports data transfers at up to 1000
kHz. The actual maximum frequency is limited by the bus capacitances (C
L
),the pull-
up resistors (R
P
), (which affect the rise and fall time of SDA and SCL, see
Table 2-12
on page 2-26), and by the input filters.
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