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參數(shù)資料
| 型號(hào)： | XC9572XL-10TQ100C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | XC9572XL High Performance CPLD |
| 中文描述： | FLASH PLD, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 78K |
| 代理商： | XC9572XL-10TQ100C |
DS052 (v2.2) August 27, 2001
Advance Product Specification
R
DC Characteristics
(Over Recommended Operating Conditions)
AC Characteristics
Symbol
Parameter
Test Conditions
Min
Max
Units
V
OH
Output high voltage for 3.3V outputs
I
OH
=
–
4.0 mA
I
OH
=
–
1.0 mA
I
OH
=
–
100
μ
A
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100
μ
A
V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
IN
= GND
f = 1.0 MHz
2.4
-
V
Output high voltage for 2.5V outputs
2.0
-
V
Output high voltage for 1.8V outputs
90% V
CCIO
-
-
V
V
OL
Output low voltage for 3.3V outputs
0.4
V
Output low voltage for 2.5V outputs
-
0.4
V
Output low voltage for 1.8V outputs
-
0.4
V
I
IL
Input leakage low current
-
10
μ
A
I
IH
Input leakagehigh current
-
10
μ
A
C
IN
I/O capacitance
-
10
pF
I
CC
Operating Supply Current
(low power mode, active)
V
I
= GND, No load
f = 1.0 MHz
14
mA
Symbol
T
PD
T
SU
T
H
T
CO
f
SYSTEM
Parameter
XC9572XV-4
Min
-
XC9572XV-5
Min
-
XC9572XV-7
Min
-
Units
ns
Max
4.0
Max
5.0
Max
7.5
I/O to output valid
I/O setup time before GCK
2.8
-
3.5
-
4.8
-
ns
I/O hold time after GCK
0
-
0
-
0
-
ns
GCK to output valid
Multiple FB internal operating
frequency
-
-
2.8
250.0
-
-
3.5
222.2
-
-
4.5
125.0
ns
MHz
T
PSU
I/O setup time before p-term clock
input
0.8
-
1.0
-
1.6
-
ns
T
PH
T
PCO
T
OE
T
OD
T
POE
T
POD
T
AO
T
PAO
T
WLH
T
PLH
I/O hold time after p-term clock input
2.0
-
2.5
-
3.2
-
ns
P-term clock output valid
GTS to output valid
-
-
4.8
3.2
-
-
6.0
4.0
-
-
7.7
5.0
ns
ns
GTS to output disable
-
3.2
-
4.0
-
5.0
ns
Product term OE to output enabled
-
5.6
-
7.0
-
9.5
ns
Product term OE to output disabled
GSR to output valid
-
-
5.6
7.9
-
-
7.0
10.0
-
-
9.5
12.0
ns
ns
P-term S/R to output valid
-
8.5
-
10.7
-
12.6
ns
GCK pulse width (High or Low)
2.0
-
2.2
-
4.0
-
ns
P-term clock pulse width (High or Low)
5.0
-
5.0
-
6.5
-
ns
Advance Information
Preliminary Information
Notes:
1.
Please contact Xilinx for up-to-date information on advance specifications.
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