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XC9572XV High-performance CPLD
DS052 (v2.2) August 27, 2001
Advance Product Specification
1-800-255-7778 R Internal Timing
Parameters
Figure 3:
AC Load Circuit
R
1
V
TEST
C
L
R
2
Device Output
Output Type
V
TEST
3.3V
2.5V
1.8V
R
1
320
250
10K
R
2
360
660
14K
C
L
35 pF
35 pF
35 pF
DS051_03_0601000
V
CCIO
3.3V
2.5V
1.8V
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
Product Term Control Delays
T
PTCK
Product term clock delay
T
PTSR
Product term set/reset delay
T
PTTS
Product term 3-state delay
Internal Register and Combinatorial Delays
T
PDI
Combinatorial logic propagation delay
T
SUI
Register setup time
T
HI
Register hold time
T
ECSU
Register clock enable setup time
T
ECHO
Register clock enable hold time
T
COI
Register clock to output valid time
T
AOI
Register async. S/R to output delay
T
RAI
Register async. S/R recover before clock
T
LOGI
Internal logic delay
T
LOGILP
Internal low power logic delay
Feedback Delays
T
F
FastCONNECT II
feedback delay
Time Adders
T
PTA
Incremental product term allocator delay
T
PTA2
Adjacent macrocell p-term allocator delay
T
SLEW
Slew-rate limited delay
Parameter
XC9572XV-4
Min
XC9572XV-5
Min
XC9572XV-7
Min
Units
Max
Max
Max
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
-
1.6
1.0
1.6
3.2
1.6
0
-
-
-
-
-
-
2.0
1.2
2.0
4.0
2.1
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
ns
ns
ns
ns
ns
ns
-
-
-
1.4
0.6
4.0
-
-
-
1.7
0.7
5.0
-
-
-
2.4
1.4
7.2
ns
ns
ns
-
0.2
-
-
-
-
0.2
4.7
-
0.2
-
-
-
-
0.2
5.9
-
1.3
-
-
-
-
0.5
6.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.6
1.2
1.6
1.2
-
-
4.0
-
-
2.0
1.5
2.0
1.5
-
-
5.0
-
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
0.6
5.6
0.7
5.7
1.4
6.4
-
1.6
-
1.6
-
3.5
ns
-
-
-
0.6
0.2
3.0
-
-
-
0.7
0.3
3.0
-
-
-
0.8
0.3
4.0
ns
ns
ns
Advance Information
Preliminary Information
Notes:
1.
Please contact Xilinx for up-to-date information on advance specifications.