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參數(shù)資料
| 型號(hào)： | MAX8543 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125 |
| 中文描述： | 降壓型控制器，具有預(yù)偏置啟動(dòng)、無損檢測、同步整流和OVP |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 399K |
| 代理商： | MAX8543 |
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M
S tep-Down Controllers with Prebias S tartup,
Lossless S ensing, S ync hronization, and OV P
______________________________________________________________________________________
21
MOS FET S elec tion
The MAX8543/MAX8544 drive two or four external,
logic-level, n-channel MOSFETs as the circuit switch
elements. The key selection parameters are:
1)
On-resistance (R
DS(ON)
): the lower, the better.
2)
Maximum drain-to-source voltage (V
DSS
): should
be at least 20% higher than the input supply rail at
the high-side MOSFET’s drain.
3)
Gate charges (Q
G
, Q
GD
, Q
GS
): the lower, the better.
For a 3.3V input application, choose a MOSFET with a
rated R
DS(ON)
at V
GS
= 2.5V. For a 5V input application,
choose the MOSFETs with rated R
DS(ON)
at V
GS
≤
4.5V.
For a good compromise between efficiency and cost,
choose the high-side MOSFET (N1, N2) that has conduc-
tion losses equal to the switching loss at nominal input
voltage and output current. The selected low-side
MOSFET (N3, N4) must have an R
DS(ON)
that satisfies the
current-limit-setting condition above. Ensure that the low-
side MOSFET does not spuriously turn on due to dV/dt
caused by the high-side MOSFET turning on as this
would result in shoot-through current and degrade the
efficiency. MOSFETs with a lower Q
GD
/ Q
GS
ratio have
higher immunity to dV/dt. For high-current applications, it
is often preferable to parallel two MOSFETs rather than to
use a single large MOSFET.
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, maximum output current,
and worst-case input voltage (for the low-side MOSFET,
worst case is at V
IN(MAX)
; for the high-side MOSFET, it
could be either at V
IN(MAX)
or V
IN(MIN)
). The high-side
and low-side MOSFETs have different loss components
due to the circuit operation. The low-side MOSFET oper-
ates as a zero-voltage switch; therefore, major losses
are the channel-conduction loss (P
LSCC
) and the body-
diode conduction loss (P
LSDC
):
Use R
DS(ON)
at T
J (MAX)
:
where V
F
is the body-diode forward-voltage drop, t
DT
is
the dead time between high-side and low-side switching
transitions, and f
S
is the switching frequency.
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses: the channel-
conduction loss (P
HSCC
), the VI overlapping switching
loss (P
HSSW
), and the drive loss (P
HSDR
). The high-side
MOSFET does not have body-diode conduction loss
because the diode never conducts current:
Use R
DS(ON)
at T
J (MAX)
:
where I
GATE
is the average DH-driver output current
capability determined by:
where R
DS(ON)(HS)
is the high-side MOSFET driver’s
on-resistance (1
, typ) and R
GATE
is the internal gate
resistance of the MOSFET (
≈
0.5
to 3
):
where V
GS
≈
V
VL.
In addition to the losses above, allow about 20% more for
additional losses due to MOSFET output capacitances
and low-side MOSFET body-diode reverse-recovery
charge dissipated in the high-side MOSFET, but it is not
well defined in the MOSFET data sheet. Refer to the
MOSFET data sheet for thermal resistance specifications
to calculate the PC board area needed to maintain the
desired maximum operating junction temperature with the
above calculated power dissipations.
To reduce EMI caused by switching noise, add a 0.1μF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DH and DL to slow down the switching transitions.
However, adding series resistors increases the power
dissipation of the MOSFET, so be sure this does not
overheat the MOSFET.
P
Q
V
f
R
+
R
R
HSDR
G
GS
S
GATE
DS ON HS
(
GATE
=
×
×
×
)(
)
I
V
+
R
R
GATE
VL
DS ON HS
(
GATE
0 5
)(
)
P
V
I
Q
Q
I
f
HSSW
IN
LOAD
GS
GD
GATE
S
=
×
×
+
×
P
V
V
I
R
HSCC
OUT
IN
LOAD
DS ON
(
=
×
×
)
2
P
I
V
t
f
LSDC
LOAD
F
DT
S
=
×
×
×
2
P
V
V
I
R
LSCC
OUT
IN
LOAD
DS ON
(
=
×
×
1
2
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX8544 | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 20-LCCC -55 to 125 |
| MAX8546EUB | PLASTIC ENCAPSULATED DEVICES |
| MAX8556 | 3-Line To 8-Line Decoders/Demultiplexers 16-CFP -55 to 125 |
| MAX8556ETE | 3-Line To 8-Line Decoders/Demultiplexers 20-LCCC -55 to 125 |
| MAX8557 | 3-Line To 8-Line Decoders/Demultiplexers 16-CFP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX8543EEE | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| MAX8543EEE+ | 功能描述:電流型 PWM 控制器 Step-Down Controller RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| MAX8543EEE+T | 功能描述:電流型 PWM 控制器 Step-Down Controller RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時(shí)間: 下降時(shí)間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| MAX8543EEE-T | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| MAX8544EEP | 功能描述:DC/DC 開關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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