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參數(shù)資料
| 型號(hào)： | XC7336-10 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 36-Macrocell CMOS EPLD |
| 中文描述： | 36宏單元的CMOS可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | XC7336-10 |
2-6
Figure 7. Input/Output Schematic (except XC7318/XC7336 which do not include I/O flip-flops)
Feedback
to UIM
Macrocell
From FB
Macrocell
Register
From FB
Macrocell
Register
Fast OE0
I/O. FCLK/O, CKEN/O
and FOE/O
Pins Only
Q
D
CLK
Q
D
EN
FastCLK1
FastCLK2
To UIM
To Function Block
AND-Array (on
Fast Input
Pins Only)
Input and
I/O Pins Only
Input
Polarity
Output
Polarity
Pin
Driver
M
M
Global
Select
X5463
FastCLK0
CKEN0
CKEN1
Q
D
CLK
EN
Fast OE1
I/O Pin
I
OL
= 24 mA
Each UIM input can be programmed to connect to any UIM
output. The delay through the interconnect matrix is con-
stant, regardless of the routing distance, fan-out, or fan-in.
When multiple inputs are programmed to be connected to
the same output, this output produces the logical AND of
the input signals. By choosing the appropriate signal
inversions at the input pins, Macrocell outputs and Func-
tion Block AND-array input, this AND logic can also be
used to implement wide NAND, OR or NOR functions.
This offers an additional level of logic without any speed
penalty.
A Macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Programming several such Macrocell outputs onto the
same UIM output emulates a 3-state bus line. If one of the
Macrocell outputs is enabled, the UIM output assumes
the enabled output’s level.
Input/Output Blocks
Macrocells drive chip outputs directly through 3-state out-
put buffers, each individually controlled by the Output
Enable product term mentioned above. The Macrocell
output can be inverted. An additional configuration option
allows the output to be disabled permanently. Two dedi-
cated FastOE inputs can also be configured to control
any of the chip outputs instead of, or in conjunction with,
the individual Output Enable product term. See Figure 7.
making the Q output identical to the D input, independent
of the clock, or as a conventional flip-flop.
The Macrocell clock source is programmable and can be
one of the private product terms or one of two global Fast-
CLK signals (FCLK0 and FCLK1). Global FastCLK sig-
nals are distributed to every Macrocell flip-flop with short
delay and minimal skew.
The asynchronous Set and Reset product terms override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set.
In addition to driving the chip output buffer, the Macrocell
output is routed back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output buffer and/or the feedback to the
UIM. If it is configured to control UIM feedback, the Output
Enable product term forces the UIM feedback line High
when the Macrocell output is disabled.
Universal Interconnect Matrix
The UIM receives inputs from each Macrocell output, I/O
pin, and dedicated input pin. Acting as an unrestricted
crossbar switch, the UIM generates 21 output signals to
each High-Density Function Block and 24 output signals
to each Fast Function Block.
This document was created with FrameMaker 4 0 2
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| XC7336-10PC44C | 制造商:Xilinx 功能描述: |
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