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參數(shù)資料
| 型號： | XC73144-12 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 144-Macrocell CMOS EPLD |
| 中文描述： | 144宏單元的CMOS可編程邏輯器件 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 117K |
| 代理商： | XC73144-12 |
XC7300 EPLD Family
2-2
mize power dissipation. Designers can operate speed-criti-
cal paths at maximum performance, while non-critical
paths dissipate less power.
Xilinx development software supports XC7300 EPLD
design using third-party schematic entry tools, HDL com-
pilers, or direct equation-based text files. Using a PC or a
workstation and one of these design capture methods,
designs are automatically mapped to an XC7300 EPLD in
a matter of minutes.
The XC7300 devices are available in plastic and ceramic
leaded chip carriers, pin-grid-array (PGA), ball-grid-array
(BGA), and quad flat pack (QFP) packages. Package
options include both windowed ceramic for design proto-
types and one-time programmable plastic versions for
cost-effective production volume.
Architecture
The XC7300 architecture consists of multiple programma-
ble Function Blocks interconnected by a UIM as shown in
Figure 1. The Dual-Block architecture contains two types of
function blocks: Fast Function Blocks and High-Density
Function Blocks. Both types of function blocks, and the I/O
blocks, are interconnected through the UIM.
Fast Function Blocks
The Fast Function Block has 24 inputs which can be indi-
vidually selected from the UIM, 12 fast input pins, or the
nine Macrocell feedbacks from the Fast Function Block.
The programmable AND array in each Fast Function Block
generates 45 product terms to drive the nine Macrocells in
each Fast Function Block. Each Macrocell can be config-
ured for registered or combinatorial logic. See Figure 2.
Five product terms from the programmable AND array are
allocated to each Macrocell. Four of these product terms
are ORed together and may be optionally inverted before
driving the input of a programmable D-type flip-flop. The
fifth product term drives the asynchronous active-High pro-
grammable Reset or Set Input to the Macrocell flip-flop.
The flip-flop can be configured as a D-type or Toggle flip-
flop, or transparent for combinatorial outputs.
Two fast function block Macrocell differences exist when
comparing the XC7336 FFB to the XC7354, XC7372 and
XC73108 FFBs.
In the XC7336, five product terms from the programmable
AND array are allocated to each Macrocell. Four of these
product-terms are OR’d together and may be optionally
inverted before driving the input of a programmable D-type
flip-flop. The fifth product-term drives the asynchronous
active High programmable Set or Reset input to the Macro-
cell flip-flop. The flip-flop can be configured as a D-type or
Toggle flip-flop, or transparent for combinatorial outputs.
See Figure 2.
In the XC7354, XC7372 and XC73108, five product terms
from the programmable AND array are allocated to each
Macrocell. Four of these product-terms are OR’d together,
inverted and drive the input of a programmable D-type flip-
flop. The fifth product-term drives the asynchronous active
High programmable Set input to the Macrocell flip-flop. The
flip-flop can be configured as a D-type flip-flop or transpar-
ent for combinatorial outputs. See Figure 3.
Figure 1. XC7300 Device Block Diagram
Input
Output
FFB
I/O
Block
FB
FB
UIM
FB
FB
I/O
Block
FFB
Output
X3204
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC73144-15 | 144-Macrocell CMOS EPLD |
| XC73144-7 | 144-Macrocell CMOS EPLD |
| XC73144-7PQ160C | 144-Macrocell CMOS EPLD |
| XC7318 | XC7300 CMOS EPLD Family |
| XC7336 | XC7300 CMOS EPLD Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC73144-12BG225I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| XC73144-12PQ160I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| XC73144-12WB225C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| XC73144-12WB225I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| XC73144-15 | 制造商:XILINX 制造商全稱:XILINX 功能描述:144-Macrocell CMOS EPLD |
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