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參數(shù)資料
| 型號(hào)： | XC7300FM |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC7300 CMOS EPLD Family |
| 中文描述： | XC7300系列可編程邏輯器件的CMOS |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 117K |
| 代理商： | XC7300FM |
2-5
Table 1. Function Generator Logic Operations
Function
D1:+: D2
D1 * D2
D1 + D2
D1
D1
D1 * D2
D1 + D2
D1:+: D2
D1 * D2
D1 + D2
D2
D2
D1 * D2
D1 + D2
X3206
Carry Input
D1
D2
Function
Generator
To Macrocell
Flip-Flop
D1
Sum-of-
Products
D2
Sum-of-
Products
Arithmetic
Carry Control
Carry Output
0
1
Arithmetic Logic Unit (ALU)
Therefore, the ALU can implement one additional layer
of logic without any speed penalty.
In arithmetic mode, the ALU block can be programmed to
generate the arithmetic sum or difference of the D1 and
D2 inputs. Combined with the carry input from the next
lower Macrocell, the ALU operates as a 1-bit full adder
generating a carry output to the next higher Macrocell.
The carry chain propagates between adjacent Macrocells
and also crosses the boundaries between Function
Blocks. This dedicated carry chain overcomes the inher-
ent speed and density problems of the traditional EPLD
architecture when trying to perform arithmetic functions.
Carry Lookahead
Each Function Block provides a carry lookahead genera-
tor capable of anticipating the carry across all nine Mac-
rocells. The carry lookahead generator reduces the
ripple-carry delay of wide arithmetic functions such as
add, subtract, and magnitude compare to that of the first
nine bits, plus the carry lookahead delay of the higher-
order Function Blocks.
Macrocell Flip-Flop
The ALU block output drives the input of a programmable
D-type flip-flop. The flip-flop is triggered by the rising edge
of the clock input, but it can be configured as transparent,
Figure 5. High-Density Function Block and Macrocell Schematic
I/O
(see fig.7)
Clock
Select
Register
Trasparent
Control
Feedback
Polarity
Input-Pad
Register/Latch
(optional)
Pin
Local
Feedback
OE Control
Global
Fast OE
Arithmetic
Carry-Out to Next
Macrocell
Shift-In
from Previous MC
Shift-Out
to Next MC
To 8 More
Macrocells
* OE is forced high when P-term is not used
RESET
SET
OE*
CLOCK
5
ALU
D1
D2
C
C
in
out
F
R
D
S
Q
M
Fast
Clocks
0 1
Arithmetic Carry-In from
Previous Macrocell
1 of 9 Macrocells
Feedback
Enable
Override
Feedback to UIM
Input to UIM
8
4
21
Inputs
from
UIM
3
from
Fast
Input
Pins
(FI)
AND Array
12 Sharable
P-Terms per
Function Block
5 Private
P-Terms per
Macrocell
X5485
Figure 6. ALU Schematic
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| XC73108 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC7300 CMOS EPLD Family |
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