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MSCAN Controller
Advance Information
68HC(9)12D60 — Rev 4.0
314
MSCAN Controller
MOTOROLA
sent successfully. The flag is also set by the msCAN12 when the
transmission request was successfully aborted due to a pending abort
request (
msCAN12 Transmitter Control Register (CTCR)
). If not masked,
a transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx flag (see
above). When a TXEx flag is set, the corresponding ABTRQx bit is
cleared (see
msCAN12 Transmitter Control Register (CTCR)
).
0 = The associated message buffer is full (loaded with a message
due for transmission).
1 = The associated message buffer is empty (not scheduled).
WARNING:
To ensure data integrity, no registers of the transmit buffers should be written
to while the associated TXE flag is cleared.
NOTE:
The CTFLG register is held in the reset state if the SFTRES bit CMCR0 is set.
17.13.9 msCAN12 Transmitter Control Register (CTCR)
ABTRQ2 – ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that a scheduled message
buffer (TXEx = 0) shall be aborted. The msCAN12 grants the request
if the message has not already started transmission, or if the
transmission is not successful (lost arbitration or error). When a
message is aborted the associated TXE and the Abort Acknowledge
flag (ABTAK, see
msCAN12 Transmitter Flag Register (CTFLG)
) are
set and an TXE interrupt is generated if enabled. The CPU cannot
reset ABTRQx. ABTRQx is cleared implicitly whenever the
associated TXE flag is set.
0 = No abort request.
1 = Abort request pending.
Bit 7
6
5
4
3
2
1
Bit 0
CTCR
R
0
ABTRQ2
ABTRQ1
ABTRQ0
0
TXEIE2
TXEIE1
TXEIE0
$0107
W
RESET
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.